Re: illegal hardware instruction during MIPS-I ELF linuxuseremulation

[Libo Zhou]

> > More updates about this. I just disassembled the unrecognized hex by hand, 
> > and figured out that the store word and load word opcodes are not the same 
> > as specified in translate.c. While the remaining fields of those 
> > unrecognized instructions do match with the source and destination 
> > registers.

> What is your compiler/assembler versions (on both machines you used)?

I don't have access to the machine for now and I may not remember the exact 
version numbers.

The cross compiler I used is a custom compiler based on gcc 4.4.0 (vaguely 
remember). It generated MIPS-I code that didn't work on QEMU. Specifically some 
generated opcodes didn't match those in target/mips/translate.c. However, I 
just checked Wikipedia's MIPS-I opcode table and I think QEMU implements it 
correctly. The single and double floating point opcode looked a little off for 
me though, but I didn't use FP ops in my case.

On my own PC I used mipsel-linux-gnu-gcc version 7.4.0. It just worked fine on 
QEMU.