Re: [PATCH 17/21] aspeed/soc: Add AST2600 support

[Cédric Le Goater]

On 20/09/2019 06:35, Joel Stanley wrote:
> On Thu, 19 Sep 2019 at 05:52, Cédric Le Goater <address@hidden> wrote:
>>
>> Initial definitions for a simple machine using an AST2600 SoC (Cortex
>> CPU).
>>
>> The Cortex CPU and its interrupt controller are too complex to handle
>> in the common Aspeed SoC framework. We introduce a new Aspeed SoC
>> class with instance_init and realize handlers to handle the differences
>> with the AST2400 and the AST2500 SoCs. This will add extra work to
>> keep in sync both models with future extensions but it makes the code
>> clearer.
>>
>> Signed-off-by: Cédric Le Goater <address@hidden>
> 
> Reviewed-by: Joel Stanley <address@hidden>
> 
> One small addition below. If you don't resend I can do a follow up patch for 
> it:
> 
>> +
>> +static const int aspeed_soc_ast2600_irqmap[] = {
> 
>> +    [ASPEED_ETH1]      = 2,
>> +    [ASPEED_ETH2]      = 3,
> 
> We need to add ETH3 and ETH4 here. They look like this:
> 
>     [ASPEED_ETH3]      = 32,
>     [ASPEED_ETH4]      = 33,
> 

I will include them in : 

  [PATCH 19/21] aspeed: Parameterise number of MACs

Thanks,

C.