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Re: [PATCH 06/21] aspeed/timer: Add AST2600 support
From: |
Joel Stanley |
Subject: |
Re: [PATCH 06/21] aspeed/timer: Add AST2600 support |
Date: |
Fri, 20 Sep 2019 04:42:32 +0000 |
On Thu, 19 Sep 2019 at 05:50, Cédric Le Goater <address@hidden> wrote:
>
> The AST2600 timer has a third control register that is used to
> implement a set-to-clear feature for the main control register.
>
> On the AST2600, it is not configurable via 0x38 (control register 3)
> as it is on the AST2500.
>
> Based on previous work from Joel Stanley.
>
> Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Joel Stanley <address@hidden>
- [Qemu-devel] [PATCH 00/21] aspeed: Add support for the AST2600 SoC, Cédric Le Goater, 2019/09/19
- [Qemu-devel] [PATCH 01/21] aspeed/wdt: Check correct register for clock source, Cédric Le Goater, 2019/09/19
- [Qemu-devel] [PATCH 02/21] hw/sd/aspeed_sdhci: New device, Cédric Le Goater, 2019/09/19
- [Qemu-devel] [PATCH 03/21] hw: aspeed_scu: Add AST2600 support, Cédric Le Goater, 2019/09/19
- [Qemu-devel] [PATCH 04/21] aspeed/timer: Introduce an object class per SoC, Cédric Le Goater, 2019/09/19
- [Qemu-devel] [PATCH 05/21] aspeed/timer: Add support for control register 3, Cédric Le Goater, 2019/09/19
- [Qemu-devel] [PATCH 06/21] aspeed/timer: Add AST2600 support, Cédric Le Goater, 2019/09/19
- Re: [PATCH 06/21] aspeed/timer: Add AST2600 support,
Joel Stanley <=
- [Qemu-devel] [PATCH 07/21] aspeed/timer: Add support for IRQ status register on the AST2600, Cédric Le Goater, 2019/09/19
- [Qemu-devel] [PATCH 08/21] aspeed/sdmc: Introduce an object class per SoC, Cédric Le Goater, 2019/09/19
- [Qemu-devel] [PATCH 09/21] aspeed/sdmc: Add AST2600 support, Cédric Le Goater, 2019/09/19
- [Qemu-devel] [PATCH 10/21] watchdog/aspeed: Introduce an object class per SoC, Cédric Le Goater, 2019/09/19
- [Qemu-devel] [PATCH 11/21] hw: wdt_aspeed: Add AST2600 support, Cédric Le Goater, 2019/09/19
- [Qemu-devel] [PATCH 12/21] aspeed/smc: Add AST2600 support, Cédric Le Goater, 2019/09/19