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Re: [Qemu-devel] [PATCH v2 01/17] RISC-V: add vfp field in CPURISCVState
From: |
Chih-Min Chao |
Subject: |
Re: [Qemu-devel] [PATCH v2 01/17] RISC-V: add vfp field in CPURISCVState |
Date: |
Thu, 12 Sep 2019 22:53:59 +0800 |
On Thu, Sep 12, 2019 at 6:39 AM Richard Henderson <
address@hidden> wrote:
> On 9/11/19 10:51 AM, Chih-Min Chao wrote:
> > Could the VLEN be configurable in cpu initialization but not fixed in
> > compilation phase ?
> > Take the integer element as example and the difference should be the
> > stride of vfp.vreg[x] isn't continuous
>
> Do you really want an unbounded amount of vector register storage?
Hi Richard,
VLEN is implementation-defined parameter and the only limitation on spec is
that it must be power of 2.
What I prefer is the value could be adjustable in runtime.
>
> > uint8_t *mem = malloc(size)
> > for (int idx = 0; idx < 32; ++idx) {
> > vfp.vreg[idx].u64 = (void *)&mem[idx * elem];
> > vfp.vreg[idx].u32 = (void *)&mem[idx * elem];
> > vfp.vreg[idx].u16 = (void *)&mem[idx * elem];
> > }
>
> This isn't adjusting the stride of the elements. And in any case this
> would
> have to be re-adjusted for every vsetvl.
>
> Not sure about the relation with vsetvl. Could you provide an example ?
Chih-Min
>
> r~
>
[Qemu-devel] [PATCH v2 03/17] RISC-V: support vector extension csr, liuzhiwei, 2019/09/11
[Qemu-devel] [PATCH v2 02/17] RISC-V: turn on vector extension from command line by cfg.ext_v Property, liuzhiwei, 2019/09/11
[Qemu-devel] [PATCH v2 04/17] RISC-V: add vector extension configure instruction, liuzhiwei, 2019/09/11