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[Qemu-devel] [PATCH v24 20/22] Add rx-softmmu
From: |
Yoshinori Sato |
Subject: |
[Qemu-devel] [PATCH v24 20/22] Add rx-softmmu |
Date: |
Thu, 12 Sep 2019 15:06:59 +0900 |
Tested-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Yoshinori Sato <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
pick ed65c02993 target/rx: Add RX to SysEmuTarget
pick 01372568ae tests: Add rx to machine-none-test.c
[PMD: Squashed patches from Richard Henderson modifying
qapi/common.json and tests/machine-none-test.c]
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
---
configure | 8 ++++++++
default-configs/rx-softmmu.mak | 3 +++
include/exec/poison.h | 1 +
include/sysemu/arch_init.h | 1 +
arch_init.c | 2 ++
tests/machine-none-test.c | 1 +
hw/Kconfig | 1 +
7 files changed, 17 insertions(+)
create mode 100644 default-configs/rx-softmmu.mak
diff --git a/configure b/configure
index 95134c0180..30ffde1788 100755
--- a/configure
+++ b/configure
@@ -7607,6 +7607,11 @@ case "$target_name" in
gdb_xml_files="riscv-64bit-cpu.xml riscv-64bit-fpu.xml riscv-64bit-csr.xml"
target_compiler=$cross_cc_riscv64
;;
+ rx)
+ TARGET_ARCH=rx
+ bflt="yes"
+ target_compiler=$cross_cc_rx
+ ;;
sh4|sh4eb)
TARGET_ARCH=sh4
bflt="yes"
@@ -7830,6 +7835,9 @@ for i in $ARCH $TARGET_BASE_ARCH ; do
riscv*)
disas_config "RISCV"
;;
+ rx)
+ disas_config "RX"
+ ;;
s390*)
disas_config "S390"
;;
diff --git a/default-configs/rx-softmmu.mak b/default-configs/rx-softmmu.mak
new file mode 100644
index 0000000000..a3eecefb11
--- /dev/null
+++ b/default-configs/rx-softmmu.mak
@@ -0,0 +1,3 @@
+# Default configuration for rx-softmmu
+
+CONFIG_RX_VIRT=y
diff --git a/include/exec/poison.h b/include/exec/poison.h
index 955eb863ab..7b9ac361dc 100644
--- a/include/exec/poison.h
+++ b/include/exec/poison.h
@@ -26,6 +26,7 @@
#pragma GCC poison TARGET_PPC
#pragma GCC poison TARGET_PPC64
#pragma GCC poison TARGET_ABI32
+#pragma GCC poison TARGET_RX
#pragma GCC poison TARGET_S390X
#pragma GCC poison TARGET_SH4
#pragma GCC poison TARGET_SPARC
diff --git a/include/sysemu/arch_init.h b/include/sysemu/arch_init.h
index 62c6fe4cf1..6c011acc52 100644
--- a/include/sysemu/arch_init.h
+++ b/include/sysemu/arch_init.h
@@ -24,6 +24,7 @@ enum {
QEMU_ARCH_NIOS2 = (1 << 17),
QEMU_ARCH_HPPA = (1 << 18),
QEMU_ARCH_RISCV = (1 << 19),
+ QEMU_ARCH_RX = (1 << 20),
};
extern const uint32_t arch_type;
diff --git a/arch_init.c b/arch_init.c
index 0a1531124c..7a37fb2c34 100644
--- a/arch_init.c
+++ b/arch_init.c
@@ -73,6 +73,8 @@ int graphic_depth = 32;
#define QEMU_ARCH QEMU_ARCH_PPC
#elif defined(TARGET_RISCV)
#define QEMU_ARCH QEMU_ARCH_RISCV
+#elif defined(TARGET_RX)
+#define QEMU_ARCH QEMU_ARCH_RX
#elif defined(TARGET_S390X)
#define QEMU_ARCH QEMU_ARCH_S390X
#elif defined(TARGET_SH4)
diff --git a/tests/machine-none-test.c b/tests/machine-none-test.c
index 5953d31755..8bb54a6360 100644
--- a/tests/machine-none-test.c
+++ b/tests/machine-none-test.c
@@ -56,6 +56,7 @@ static struct arch2cpu cpus_map[] = {
{ "hppa", "hppa" },
{ "riscv64", "rv64gcsu-v1.10.0" },
{ "riscv32", "rv32gcsu-v1.9.1" },
+ { "rx", "rx62n" },
};
static const char *get_cpu_model_by_arch(const char *arch)
diff --git a/hw/Kconfig b/hw/Kconfig
index b45db3c813..77bbc59cc7 100644
--- a/hw/Kconfig
+++ b/hw/Kconfig
@@ -54,6 +54,7 @@ source nios2/Kconfig
source openrisc/Kconfig
source ppc/Kconfig
source riscv/Kconfig
+source rx/Kconfig
source s390x/Kconfig
source sh4/Kconfig
source sparc/Kconfig
--
2.20.1
- [Qemu-devel] [PATCH v24 13/22] target/rx: Dump bytes for each insn during disassembly, (continued)
- [Qemu-devel] [PATCH v24 13/22] target/rx: Dump bytes for each insn during disassembly, Yoshinori Sato, 2019/09/12
- [Qemu-devel] [PATCH v24 03/22] hw/registerfields.h: Add 8bit and 16bit register macros, Yoshinori Sato, 2019/09/12
- [Qemu-devel] [PATCH v24 02/22] qemu/bitops.h: Add extract8 and extract16, Yoshinori Sato, 2019/09/12
- [Qemu-devel] [PATCH v24 22/22] qapi/machine.json: Add RX cpu., Yoshinori Sato, 2019/09/12
- [Qemu-devel] [PATCH v24 11/22] target/rx: Emit all disassembly in one prt(), Yoshinori Sato, 2019/09/12
- [Qemu-devel] [PATCH v24 19/22] hw/rx: Restrict the RX62N microcontroller to the RX62N CPU core, Yoshinori Sato, 2019/09/12
- [Qemu-devel] [PATCH v24 09/22] target/rx: Replace operand with prt_ldmi in disassembler, Yoshinori Sato, 2019/09/12
- [Qemu-devel] [PATCH v24 21/22] BootLinuxConsoleTest: Test the RX-Virt machine, Yoshinori Sato, 2019/09/12
- [Qemu-devel] [PATCH v24 16/22] hw/char: RX62N serial communication interface (SCI), Yoshinori Sato, 2019/09/12
- [Qemu-devel] [PATCH v24 20/22] Add rx-softmmu,
Yoshinori Sato <=
- [Qemu-devel] [PATCH v24 08/22] target/rx: Disassemble rx_index_addr into a string, Yoshinori Sato, 2019/09/12
- [Qemu-devel] [PATCH v24 12/22] target/rx: Collect all bytes during disassembly, Yoshinori Sato, 2019/09/12
- [Qemu-devel] [PATCH v24 14/22] hw/intc: RX62N interrupt controller (ICUa), Yoshinori Sato, 2019/09/12
- [Qemu-devel] [PATCH v24 05/22] target/rx: TCG helper, Yoshinori Sato, 2019/09/12
- [Qemu-devel] [PATCH v24 15/22] hw/timer: RX62N internal timer modules, Yoshinori Sato, 2019/09/12
- [Qemu-devel] [PATCH v24 06/22] target/rx: CPU definition, Yoshinori Sato, 2019/09/12
- [Qemu-devel] [PATCH v24 07/22] target/rx: RX disassembler, Yoshinori Sato, 2019/09/12
- [Qemu-devel] [PATCH v24 17/22] hw/rx: RX Target hardware definition, Yoshinori Sato, 2019/09/12
- [Qemu-devel] [PATCH v24 04/22] target/rx: TCG translation, Yoshinori Sato, 2019/09/12