[Qemu-devel] [RFC 2 PATCH 00/16] APIC ID fixes for AMD EPYC CPU models

[Moger, Babu]

These series fixes the problems encoding APIC ID for AMD EPYC cpu models.
https://bugzilla.redhat.com/show_bug.cgi?id=1728166

This is the second pass to give an idea of the changes required to address
the issue. First pass is availabe at 
https://patchwork.kernel.org/cover/11069785/

Currently, apic id is decoded based on sockets/dies/cores/threads. This appears
to work for most standard configurations for AMD and other vendors. But this
decoding does not follow AMD's APIC ID enumeration. In some cases this
causes CPU topology inconstancy. While booting guest Kernel is trying to
validate topology. It finds the topology not aligning to EPYC models.

To fix the problem we need to build the topology as per the
Processor Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1
Processors. It is available at https://www.amd.com/en/support/tech-docs

Here is the text from the PPR.
2.1.10.2.1.3
ApicId Enumeration Requirements
Operating systems are expected to use
Core::X86::Cpuid::SizeId[ApicIdCoreIdSize], the number of least
significant bits in the Initial APIC ID that indicate core ID within a
processor, in constructing per-core CPUID
masks. Core::X86::Cpuid::SizeId[ApicIdCoreIdSize] determines the maximum number
of cores (MNC) that the
processor could theoretically support, not the actual number of cores that are
actually implemented or enabled on
the processor, as indicated by Core::X86::Cpuid::SizeId[NC].
Each Core::X86::Apic::ApicId[ApicId] register is preset as follows:
• ApicId[6] = Socket ID.
• ApicId[5:4] = Node ID.
• ApicId[3] = Logical CCX L3 complex ID
• ApicId[2:0]= (SMT) ? {LogicalCoreID[1:0],ThreadId} :
{1'b0,LogicalCoreID[1:0]}.
"""

v2:
  1. Introduced the new property epyc to enable new epyc mode.
  2. Separated the epyc mode and non epyc mode function.
  3. Introduced function pointers in PCMachineState to handle the
     differences.
  4. Mildly tested different combinations to make things are working as 
expected.
  5. TODO : Setting the epyc feature bit needs to be worked out. This feature is
     supported only on AMD EPYC models. I may need some guidance on that.

v1:
  https://patchwork.kernel.org/cover/11069785/

---

Babu Moger (16):
      numa: Split the numa functionality
      hw/i386: Rename X86CPUTopoInfo structure to X86CPUTopoIDs
      hw/i386: Introduce X86CPUTopoInfo to contain topology info
      machine: Add SMP Sockets in CpuTopology
      hw/i386: Simplify topology Offset/width Calculation
      hw/core: Add core complex id in X86CPU topology
      hw/386: Add new epyc mode topology decoding functions
      i386: Cleanup and use the new epyc mode topology functions
      hw/i386: Introduce initialize_topo_info function
      hw/i386: Introduce apicid_from_cpu_idx in PCMachineState
      Introduce-topo_ids_from_apicid-handler
      hw/i386: Introduce apic_id_from_topo_ids handler in PCMachineState
      machine: Add new epyc property in PCMachineState
      hw/i386: Introduce epyc mode function handlers
      i386: Fix pkg_id offset for epyc mode
      hw/core: Fix up the machine_set_cpu_numa_node for epyc


 hw/core/machine-hmp-cmds.c |    3 
 hw/core/machine.c          |   38 ++++++
 hw/core/numa.c             |  110 ++++++++++++----
 hw/i386/pc.c               |  143 +++++++++++++++------
 include/hw/boards.h        |    8 +
 include/hw/i386/pc.h       |    9 +
 include/hw/i386/topology.h |  294 +++++++++++++++++++++++++++++++++++---------
 include/sysemu/numa.h      |    2 
 qapi/machine.json          |    4 -
 target/i386/cpu.c          |  209 +++++++++++--------------------
 target/i386/cpu.h          |    1 
 vl.c                       |    3 
 12 files changed, 560 insertions(+), 264 deletions(-)

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