[Qemu-devel] [PULL 00/13] target/openrisc updates

[Richard Henderson]

The following changes since commit a8b5ad8e1faef0d1bb3e550530328e8ec76fe87c:

  Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging 
(2019-09-04 17:22:34 +0100)

are available in the Git repository at:

  https://github.com/rth7680/qemu.git tags/pull-or1k-20190904

for you to fetch changes up to 9e3bab08d3e3f5808cc35a59af1912bfb6fe96fd:

  target/openrisc: Update cpu "any" to v1.3 (2019-09-04 13:01:56 -0700)

----------------------------------------------------------------
Updates for arch v1.3.

----------------------------------------------------------------
Richard Henderson (13):
      target/openrisc: Add DisasContext parameter to check_r0_write
      target/openrisc: Replace cpu register array with a function
      target/openrisc: Cache R0 in DisasContext
      target/openrisc: Make VR and PPC read-only
      target/openrisc: Move VR, UPR, DMMCFGR, IMMCFGR to cpu init
      target/openrisc: Add VR2 and AVR special processor registers
      target/openrisc: Fix lf.ftoi.s
      target/openrisc: Check CPUCFG_OF32S for float insns
      target/openrisc: Add support for ORFPX64A32
      target/openrisc: Implement unordered fp comparisons
      target/openrisc: Implement move to/from FPCSR
      target/openrisc: Implement l.adrp
      target/openrisc: Update cpu "any" to v1.3

 linux-user/openrisc/target_elf.h |   2 +-
 target/openrisc/cpu.h            |  24 +-
 target/openrisc/helper.h         |   6 +
 target/openrisc/cpu.c            |  30 +-
 target/openrisc/disas.c          |  81 +++++
 target/openrisc/fpu_helper.c     |  49 ++-
 target/openrisc/machine.c        |  11 +
 target/openrisc/sys_helper.c     |  38 ++-
 target/openrisc/translate.c      | 716 +++++++++++++++++++++++++++++----------
 target/openrisc/insns.decode     |  45 +++
 10 files changed, 774 insertions(+), 228 deletions(-)