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[Qemu-devel] [PATCH v4 66/69] target/arm: Convert T16, Unconditional bra
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v4 66/69] target/arm: Convert T16, Unconditional branch |
Date: |
Wed, 4 Sep 2019 12:30:56 -0700 |
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/translate.c | 9 ++-------
target/arm/t16.decode | 6 ++++++
2 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 4f4c77fc89..3238ccbf1e 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -10736,7 +10736,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t
insn)
static void disas_thumb_insn(DisasContext *s, uint32_t insn)
{
- uint32_t val;
int32_t offset;
TCGv_i32 tmp;
TCGv_i32 tmp2;
@@ -10780,12 +10779,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t
insn)
gen_bx(s, tmp);
break;
}
- /* unconditional branch */
- val = read_pc(s);
- offset = ((int32_t)insn << 21) >> 21;
- val += offset << 1;
- gen_jmp(s, val);
- break;
+ /* unconditional branch, in decodetree */
+ goto illegal_op;
case 15:
/* thumb_insn_is_16bit() ensures we can't get here for
diff --git a/target/arm/t16.decode b/target/arm/t16.decode
index 0b4da411e0..a4c89dba61 100644
--- a/target/arm/t16.decode
+++ b/target/arm/t16.decode
@@ -266,3 +266,9 @@ LDM_t16 1011 110 ......... \
SVC 1101 1111 imm:8 &i
B_cond_thumb 1101 cond:4 ........ &ci imm=%imm8_0x2
}
+
+# Unconditional Branch
+
+%imm11_0x2 0:s11 !function=times_2
+
+B 11100 ........... &i imm=%imm11_0x2
--
2.17.1
- [Qemu-devel] [PATCH v4 50/69] target/arm: Convert T16 load/store multiple, (continued)
- [Qemu-devel] [PATCH v4 50/69] target/arm: Convert T16 load/store multiple, Richard Henderson, 2019/09/04
- [Qemu-devel] [PATCH v4 47/69] target/arm: Convert T16 load/store (register offset), Richard Henderson, 2019/09/04
- [Qemu-devel] [PATCH v4 51/69] target/arm: Convert T16 add/sub (3 low, 2 low and imm), Richard Henderson, 2019/09/04
- [Qemu-devel] [PATCH v4 49/69] target/arm: Convert T16 add pc/sp (immediate), Richard Henderson, 2019/09/04
- [Qemu-devel] [PATCH v4 54/69] target/arm: Convert T16 add, compare, move (two high registers), Richard Henderson, 2019/09/04
- [Qemu-devel] [PATCH v4 60/69] target/arm: Split gen_nop_hint, Richard Henderson, 2019/09/04
- [Qemu-devel] [PATCH v4 58/69] target/arm: Convert T16, Reverse bytes, Richard Henderson, 2019/09/04
- [Qemu-devel] [PATCH v4 52/69] target/arm: Convert T16 one low register and immediate, Richard Henderson, 2019/09/04
- [Qemu-devel] [PATCH v4 55/69] target/arm: Convert T16 adjust sp (immediate), Richard Henderson, 2019/09/04
- [Qemu-devel] [PATCH v4 66/69] target/arm: Convert T16, Unconditional branch,
Richard Henderson <=
- [Qemu-devel] [PATCH v4 68/69] target/arm: Clean up disas_thumb_insn, Richard Henderson, 2019/09/04
- [Qemu-devel] [PATCH v4 69/69] target/arm: Inline gen_bx_im into callers, Richard Henderson, 2019/09/04
- [Qemu-devel] [PATCH v4 53/69] target/arm: Convert T16 branch and exchange, Richard Henderson, 2019/09/04
- [Qemu-devel] [PATCH v4 57/69] target/arm: Convert T16, Change processor state, Richard Henderson, 2019/09/04
- [Qemu-devel] [PATCH v4 59/69] target/arm: Convert T16, nop hints, Richard Henderson, 2019/09/04
- [Qemu-devel] [PATCH v4 63/69] target/arm: Convert T16, Miscellaneous 16-bit instructions, Richard Henderson, 2019/09/04
- [Qemu-devel] [PATCH v4 64/69] target/arm: Convert T16, shift immediate, Richard Henderson, 2019/09/04
- [Qemu-devel] [PATCH v4 67/69] target/arm: Convert T16, long branches, Richard Henderson, 2019/09/04
- [Qemu-devel] [PATCH v4 62/69] target/arm: Convert T16, Conditional branches, Supervisor call, Richard Henderson, 2019/09/04