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[Qemu-devel] [PATCH v4 22/69] target/arm: Diagnose UNPREDICTABLE ldrex/s
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v4 22/69] target/arm: Diagnose UNPREDICTABLE ldrex/strex cases |
Date: |
Wed, 4 Sep 2019 12:30:12 -0700 |
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/translate.c | 40 ++++++++++++++++++++++++++++++++++++++--
1 file changed, 38 insertions(+), 2 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index ec80c9cbbc..9338873a4a 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -8912,6 +8912,18 @@ static bool op_strex(DisasContext *s, arg_STREX *a,
MemOp mop, bool rel)
{
TCGv_i32 addr;
+ /* We UNDEF for these UNPREDICTABLE cases. */
+ if (a->rd == 15 || a->rn == 15 || a->rt == 15
+ || a->rd == a->rn || a->rd == a->rt
+ || (s->thumb && (a->rd == 13 || a->rt == 13))
+ || (mop == MO_64
+ && (a->rt2 == 15
+ || a->rd == a->rt2 || a->rt == a->rt2
+ || (s->thumb && a->rt2 == 13)))) {
+ unallocated_encoding(s);
+ return true;
+ }
+
if (rel) {
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
}
@@ -8938,6 +8950,7 @@ static bool trans_STREXD_a32(DisasContext *s, arg_STREX
*a)
if (!ENABLE_ARCH_6K) {
return false;
}
+ /* We UNDEF for these UNPREDICTABLE cases. */
if (a->rt & 1) {
unallocated_encoding(s);
return true;
@@ -8980,6 +8993,7 @@ static bool trans_STLEXD_a32(DisasContext *s, arg_STREX
*a)
if (!ENABLE_ARCH_8) {
return false;
}
+ /* We UNDEF for these UNPREDICTABLE cases. */
if (a->rt & 1) {
unallocated_encoding(s);
return true;
@@ -9019,8 +9033,13 @@ static bool op_stl(DisasContext *s, arg_STL *a, MemOp
mop)
if (!ENABLE_ARCH_8) {
return false;
}
- addr = load_reg(s, a->rn);
+ /* We UNDEF for these UNPREDICTABLE cases. */
+ if (a->rn == 15 || a->rt == 15) {
+ unallocated_encoding(s);
+ return true;
+ }
+ addr = load_reg(s, a->rn);
tmp = load_reg(s, a->rt);
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
gen_aa32_st_i32(s, tmp, addr, get_mem_index(s), mop | s->be_data);
@@ -9050,6 +9069,16 @@ static bool op_ldrex(DisasContext *s, arg_LDREX *a,
MemOp mop, bool acq)
{
TCGv_i32 addr;
+ /* We UNDEF for these UNPREDICTABLE cases. */
+ if (a->rn == 15 || a->rt == 15
+ || (s->thumb && a->rt == 13)
+ || (mop == MO_64
+ && (a->rt2 == 15 || a->rt == a->rt2
+ || (s->thumb && a->rt2 == 13)))) {
+ unallocated_encoding(s);
+ return true;
+ }
+
addr = tcg_temp_local_new_i32();
load_reg_var(s, addr, a->rn);
tcg_gen_addi_i32(addr, addr, a->imm);
@@ -9076,6 +9105,7 @@ static bool trans_LDREXD_a32(DisasContext *s, arg_LDREX
*a)
if (!ENABLE_ARCH_6K) {
return false;
}
+ /* We UNDEF for these UNPREDICTABLE cases. */
if (a->rt & 1) {
unallocated_encoding(s);
return true;
@@ -9118,6 +9148,7 @@ static bool trans_LDAEXD_a32(DisasContext *s, arg_LDREX
*a)
if (!ENABLE_ARCH_8) {
return false;
}
+ /* We UNDEF for these UNPREDICTABLE cases. */
if (a->rt & 1) {
unallocated_encoding(s);
return true;
@@ -9157,8 +9188,13 @@ static bool op_lda(DisasContext *s, arg_LDA *a, MemOp
mop)
if (!ENABLE_ARCH_8) {
return false;
}
- addr = load_reg(s, a->rn);
+ /* We UNDEF for these UNPREDICTABLE cases. */
+ if (a->rn == 15 || a->rt == 15) {
+ unallocated_encoding(s);
+ return true;
+ }
+ addr = load_reg(s, a->rn);
tmp = tcg_temp_new_i32();
gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), mop | s->be_data);
disas_set_da_iss(s, mop, a->rt | ISSIsAcqRel);
--
2.17.1
- Re: [Qemu-devel] [PATCH v4 10/69] target/arm: Simplify op_smlaxxx for SMLAL*, (continued)
- [Qemu-devel] [PATCH v4 09/69] target/arm: Convert Halfword multiply and multiply accumulate, Richard Henderson, 2019/09/04
- [Qemu-devel] [PATCH v4 12/69] target/arm: Convert MSR (immediate) and hints, Richard Henderson, 2019/09/04
- [Qemu-devel] [PATCH v4 16/69] target/arm: Convert CLZ, Richard Henderson, 2019/09/04
- [Qemu-devel] [PATCH v4 13/69] target/arm: Convert MRS/MSR (banked, register), Richard Henderson, 2019/09/04
- [Qemu-devel] [PATCH v4 14/69] target/arm: Convert Cyclic Redundancy Check, Richard Henderson, 2019/09/04
- [Qemu-devel] [PATCH v4 15/69] target/arm: Convert BX, BXJ, BLX (register), Richard Henderson, 2019/09/04
- [Qemu-devel] [PATCH v4 19/69] target/arm: Convert T32 ADDW/SUBW, Richard Henderson, 2019/09/04
- [Qemu-devel] [PATCH v4 17/69] target/arm: Convert ERET, Richard Henderson, 2019/09/04
- [Qemu-devel] [PATCH v4 18/69] target/arm: Convert the rest of A32 Miscelaneous instructions, Richard Henderson, 2019/09/04
- [Qemu-devel] [PATCH v4 22/69] target/arm: Diagnose UNPREDICTABLE ldrex/strex cases,
Richard Henderson <=
- [Qemu-devel] [PATCH v4 21/69] target/arm: Convert Synchronization primitives, Richard Henderson, 2019/09/04
- [Qemu-devel] [PATCH v4 23/69] target/arm: Convert USAD8, USADA8, SBFX, UBFX, BFC, BFI, UDF, Richard Henderson, 2019/09/04
- [Qemu-devel] [PATCH v4 24/69] target/arm: Convert Parallel addition and subtraction, Richard Henderson, 2019/09/04
- [Qemu-devel] [PATCH v4 27/69] target/arm: Convert MOVW, MOVT, Richard Henderson, 2019/09/04
- [Qemu-devel] [PATCH v4 29/69] target/arm: Diagnose writeback register in list for LDM for v7, Richard Henderson, 2019/09/04
- [Qemu-devel] [PATCH v4 20/69] target/arm: Convert load/store (register, immediate, literal), Richard Henderson, 2019/09/04
- [Qemu-devel] [PATCH v4 31/69] target/arm: Diagnose base == pc for LDM/STM, Richard Henderson, 2019/09/04
- [Qemu-devel] [PATCH v4 30/69] target/arm: Diagnose too few registers in list for LDM/STM, Richard Henderson, 2019/09/04
- [Qemu-devel] [PATCH v4 26/69] target/arm: Convert Signed multiply, signed and unsigned divide, Richard Henderson, 2019/09/04
- [Qemu-devel] [PATCH v4 28/69] target/arm: Convert LDM, STM, Richard Henderson, 2019/09/04