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[Qemu-devel] [PATCH 35/36] tcg: Make probe_write() return a pointer to t
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 35/36] tcg: Make probe_write() return a pointer to the host page |
Date: |
Tue, 3 Sep 2019 09:08:57 -0700 |
From: David Hildenbrand <address@hidden>
... similar to tlb_vaddr_to_host(); however, allow access to the host
page except when TLB_NOTDIRTY or TLB_MMIO is set.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: David Hildenbrand <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
include/exec/exec-all.h | 4 ++--
accel/tcg/cputlb.c | 21 ++++++++++++++++-----
accel/tcg/user-exec.c | 6 ++++--
3 files changed, 22 insertions(+), 9 deletions(-)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index cbcc85add3..a7893ed16b 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -310,8 +310,8 @@ static inline void
tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu,
{
}
#endif
-void probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_idx,
- uintptr_t retaddr);
+void *probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_idx,
+ uintptr_t retaddr);
#define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line
*/
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 707adf7631..cb969d8372 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -1078,11 +1078,11 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env,
target_ulong addr)
/* Probe for whether the specified guest write access is permitted.
* If it is not permitted then an exception will be taken in the same
* way as if this were a real write access (and we will not return).
- * Otherwise the function will return, and there will be a valid
- * entry in the TLB for this access.
+ * If the size is 0 or the page requires I/O access, returns NULL; otherwise,
+ * returns the address of the host page similar to tlb_vaddr_to_host().
*/
-void probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_idx,
- uintptr_t retaddr)
+void *probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_idx,
+ uintptr_t retaddr)
{
uintptr_t index = tlb_index(env, mmu_idx, addr);
CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr);
@@ -1101,12 +1101,23 @@ void probe_write(CPUArchState *env, target_ulong addr,
int size, int mmu_idx,
tlb_addr = tlb_addr_write(entry);
}
+ if (!size) {
+ return NULL;
+ }
+
/* Handle watchpoints. */
- if ((tlb_addr & TLB_WATCHPOINT) && size > 0) {
+ if (tlb_addr & TLB_WATCHPOINT) {
cpu_check_watchpoint(env_cpu(env), addr, size,
env_tlb(env)->d[mmu_idx].iotlb[index].attrs,
BP_MEM_WRITE, retaddr);
}
+
+ if (tlb_addr & (TLB_NOTDIRTY | TLB_MMIO)) {
+ /* I/O access */
+ return NULL;
+ }
+
+ return (void *)((uintptr_t)addr + entry->addend);
}
void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr,
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index 625c33f893..5720bf8056 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -188,8 +188,8 @@ static inline int handle_cpu_signal(uintptr_t pc, siginfo_t
*info,
g_assert_not_reached();
}
-void probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_idx,
- uintptr_t retaddr)
+void *probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_idx,
+ uintptr_t retaddr)
{
g_assert(-(addr | TARGET_PAGE_MASK) >= size);
@@ -202,6 +202,8 @@ void probe_write(CPUArchState *env, target_ulong addr, int
size, int mmu_idx,
retaddr);
g_assert_not_reached();
}
+
+ return size ? g2h(addr) : NULL;
}
#if defined(__i386__)
--
2.17.1
- [Qemu-devel] [PATCH 25/36] cputlb: Remove double-alignment in store_helper, (continued)
- [Qemu-devel] [PATCH 25/36] cputlb: Remove double-alignment in store_helper, Richard Henderson, 2019/09/03
- [Qemu-devel] [PATCH 27/36] tcg: Check for watchpoints in probe_write(), Richard Henderson, 2019/09/03
- [Qemu-devel] [PATCH 29/36] s390x/tcg: Fix length calculation in probe_write_access(), Richard Henderson, 2019/09/03
- [Qemu-devel] [PATCH 26/36] cputlb: Handle watchpoints via TLB_WATCHPOINT, Richard Henderson, 2019/09/03
- [Qemu-devel] [PATCH 28/36] s390x/tcg: Use guest_addr_valid() instead of h2g_valid() in probe_write_access(), Richard Henderson, 2019/09/03
- [Qemu-devel] [PATCH 30/36] tcg: Factor out CONFIG_USER_ONLY probe_write() from s390x code, Richard Henderson, 2019/09/03
- [Qemu-devel] [PATCH 31/36] tcg: Enforce single page access in probe_write(), Richard Henderson, 2019/09/03
- [Qemu-devel] [PATCH 32/36] mips/tcg: Call probe_write() for CONFIG_USER_ONLY as well, Richard Henderson, 2019/09/03
- [Qemu-devel] [PATCH 33/36] hppa/tcg: Call probe_write() also for CONFIG_USER_ONLY, Richard Henderson, 2019/09/03
- [Qemu-devel] [PATCH 34/36] s390x/tcg: Pass a size to probe_write() in do_csst(), Richard Henderson, 2019/09/03
- [Qemu-devel] [PATCH 35/36] tcg: Make probe_write() return a pointer to the host page,
Richard Henderson <=
- [Qemu-devel] [PATCH 36/36] tcg: Factor out probe_write() logic into probe_access(), Richard Henderson, 2019/09/03
- Re: [Qemu-devel] [PATCH 00/36] tcg patch queue, Mark Cave-Ayland, 2019/09/03
- Re: [Qemu-devel] [PATCH 00/36] tcg patch queue, Philippe Mathieu-Daudé, 2019/09/03
- Re: [Qemu-devel] [PATCH 00/36] tcg patch queue, Peter Maydell, 2019/09/04