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[Qemu-devel] [PATCH 24/36] cputlb: Fix size operand for tlb_fill on unal
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 24/36] cputlb: Fix size operand for tlb_fill on unaligned store |
Date: |
Tue, 3 Sep 2019 09:08:46 -0700 |
We are currently passing the size of the full write to
the tlb_fill for the second page. Instead pass the real
size of the write to that page.
This argument is unused within all tlb_fill, except to be
logged via tracing, so in practice this makes no difference.
But in a moment we'll need the value of size2 for watchpoints,
and if we've computed the value we might as well use it.
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: David Hildenbrand <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
accel/tcg/cputlb.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index c9576bebcf..7fb67d2f05 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -1504,6 +1504,8 @@ store_helper(CPUArchState *env, target_ulong addr,
uint64_t val,
uintptr_t index2;
CPUTLBEntry *entry2;
target_ulong page2, tlb_addr2;
+ size_t size2;
+
do_unaligned_access:
/*
* Ensure the second page is in the TLB. Note that the first page
@@ -1511,13 +1513,14 @@ store_helper(CPUArchState *env, target_ulong addr,
uint64_t val,
* cannot evict the first.
*/
page2 = (addr + size) & TARGET_PAGE_MASK;
+ size2 = (addr + size) & ~TARGET_PAGE_MASK;
index2 = tlb_index(env, mmu_idx, page2);
entry2 = tlb_entry(env, mmu_idx, page2);
tlb_addr2 = tlb_addr_write(entry2);
if (!tlb_hit_page(tlb_addr2, page2)
&& !victim_tlb_hit(env, mmu_idx, index2, tlb_off,
page2 & TARGET_PAGE_MASK)) {
- tlb_fill(env_cpu(env), page2, size, MMU_DATA_STORE,
+ tlb_fill(env_cpu(env), page2, size2, MMU_DATA_STORE,
mmu_idx, retaddr);
}
--
2.17.1
- [Qemu-devel] [PATCH 13/36] exec: Hard code size with MO_{8|16|32|64}, (continued)
- [Qemu-devel] [PATCH 13/36] exec: Hard code size with MO_{8|16|32|64}, Richard Henderson, 2019/09/03
- [Qemu-devel] [PATCH 01/36] tcg: TCGMemOp is now accelerator independent MemOp, Richard Henderson, 2019/09/03
- [Qemu-devel] [PATCH 15/36] cputlb: Replace size and endian operands for MemOp, Richard Henderson, 2019/09/03
- [Qemu-devel] [PATCH 14/36] memory: Access MemoryRegion with endianness, Richard Henderson, 2019/09/03
- [Qemu-devel] [PATCH 16/36] memory: Single byte swap along the I/O path, Richard Henderson, 2019/09/03
- [Qemu-devel] [PATCH 19/36] target/sparc: sun4u Invert Endian TTE bit, Richard Henderson, 2019/09/03
- [Qemu-devel] [PATCH 18/36] target/sparc: Add TLB entry with attributes, Richard Henderson, 2019/09/03
- [Qemu-devel] [PATCH 20/36] exec: Move user-only watchpoint stubs inline, Richard Henderson, 2019/09/03
- [Qemu-devel] [PATCH 21/36] exec: Factor out core logic of check_watchpoint(), Richard Henderson, 2019/09/03
- [Qemu-devel] [PATCH 17/36] cputlb: Byte swap memory transaction attribute, Richard Henderson, 2019/09/03
- [Qemu-devel] [PATCH 24/36] cputlb: Fix size operand for tlb_fill on unaligned store,
Richard Henderson <=
- [Qemu-devel] [PATCH 23/36] exec: Factor out cpu_watchpoint_address_matches, Richard Henderson, 2019/09/03
- [Qemu-devel] [PATCH 22/36] cputlb: Fold TLB_RECHECK into TLB_INVALID_MASK, Richard Henderson, 2019/09/03
- [Qemu-devel] [PATCH 25/36] cputlb: Remove double-alignment in store_helper, Richard Henderson, 2019/09/03
- [Qemu-devel] [PATCH 27/36] tcg: Check for watchpoints in probe_write(), Richard Henderson, 2019/09/03
- [Qemu-devel] [PATCH 29/36] s390x/tcg: Fix length calculation in probe_write_access(), Richard Henderson, 2019/09/03
- [Qemu-devel] [PATCH 26/36] cputlb: Handle watchpoints via TLB_WATCHPOINT, Richard Henderson, 2019/09/03
- [Qemu-devel] [PATCH 28/36] s390x/tcg: Use guest_addr_valid() instead of h2g_valid() in probe_write_access(), Richard Henderson, 2019/09/03
- [Qemu-devel] [PATCH 30/36] tcg: Factor out CONFIG_USER_ONLY probe_write() from s390x code, Richard Henderson, 2019/09/03