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Re: [Qemu-devel] [PATCH v6 15/30] riscv: hart: Add a "hartid-base" prope
From: |
Alistair Francis |
Subject: |
Re: [Qemu-devel] [PATCH v6 15/30] riscv: hart: Add a "hartid-base" property to RISC-V hart array |
Date: |
Fri, 30 Aug 2019 14:18:21 -0700 |
On Tue, Aug 27, 2019 at 8:12 AM Bin Meng <address@hidden> wrote:
>
> At present each hart's hartid in a RISC-V hart array is assigned
> the same value of its index in the hart array. But for a system
> that has multiple hart arrays, this is not the case any more.
>
> Add a new "hartid-base" property so that hartid number can be
> assigned based on the property value.
>
> Signed-off-by: Bin Meng <address@hidden>
>
> ---
>
> Changes in v6:
> - use s->hartid_base directly, instead of an extra variable
>
> Changes in v5: None
> Changes in v4:
> - new patch to add a "hartid-base" property to RISC-V hart array
>
> Changes in v3: None
> Changes in v2: None
>
> hw/riscv/riscv_hart.c | 7 ++++---
> include/hw/riscv/riscv_hart.h | 1 +
> 2 files changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c
> index 9deef869..7cfc835 100644
> --- a/hw/riscv/riscv_hart.c
> +++ b/hw/riscv/riscv_hart.c
> @@ -27,6 +27,7 @@
>
> static Property riscv_harts_props[] = {
> DEFINE_PROP_UINT32("num-harts", RISCVHartArrayState, num_harts, 1),
> + DEFINE_PROP_UINT32("hartid-base", RISCVHartArrayState, hartid_base, 0),
> DEFINE_PROP_STRING("cpu-type", RISCVHartArrayState, cpu_type),
> DEFINE_PROP_END_OF_LIST(),
> };
> @@ -37,7 +38,7 @@ static void riscv_harts_cpu_reset(void *opaque)
> cpu_reset(CPU(cpu));
> }
>
> -static void riscv_hart_realize(RISCVHartArrayState *s, int idx,
> +static void riscv_hart_realize(RISCVHartArrayState *s, int idx, uint32_t
> hartid,
> char *cpu_type, Error **errp)
> {
> Error *err = NULL;
> @@ -45,7 +46,7 @@ static void riscv_hart_realize(RISCVHartArrayState *s, int
> idx,
> object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx],
> sizeof(RISCVCPU), cpu_type,
> &error_abort, NULL);
> - s->harts[idx].env.mhartid = idx;
> + s->harts[idx].env.mhartid = hartid;
Couldn't this just be `s->hartid_base + idx`?
Alistair
> qemu_register_reset(riscv_harts_cpu_reset, &s->harts[idx]);
> object_property_set_bool(OBJECT(&s->harts[idx]), true,
> "realized", &err);
> @@ -63,7 +64,7 @@ static void riscv_harts_realize(DeviceState *dev, Error
> **errp)
> s->harts = g_new0(RISCVCPU, s->num_harts);
>
> for (n = 0; n < s->num_harts; n++) {
> - riscv_hart_realize(s, n, s->cpu_type, errp);
> + riscv_hart_realize(s, n, s->hartid_base + n, s->cpu_type, errp);
> }
> }
>
> diff --git a/include/hw/riscv/riscv_hart.h b/include/hw/riscv/riscv_hart.h
> index 0671d88..1984e30 100644
> --- a/include/hw/riscv/riscv_hart.h
> +++ b/include/hw/riscv/riscv_hart.h
> @@ -32,6 +32,7 @@ typedef struct RISCVHartArrayState {
>
> /*< public >*/
> uint32_t num_harts;
> + uint32_t hartid_base;
> char *cpu_type;
> RISCVCPU *harts;
> } RISCVHartArrayState;
> --
> 2.7.4
>
>
- [Qemu-devel] [PATCH v6 13/30] riscv: Add a sifive_cpu.h to include both E and U cpu type defines, (continued)
- [Qemu-devel] [PATCH v6 13/30] riscv: Add a sifive_cpu.h to include both E and U cpu type defines, Bin Meng, 2019/08/27
- [Qemu-devel] [PATCH v6 24/30] riscv: sifive_u: Change UART node name in device tree, Bin Meng, 2019/08/27
- [Qemu-devel] [PATCH v6 11/30] riscv: sifive_e: prci: Update the PRCI register block size, Bin Meng, 2019/08/27
- [Qemu-devel] [PATCH v6 12/30] riscv: sifive_e: Drop sifive_mmio_emulate(), Bin Meng, 2019/08/27
- [Qemu-devel] [PATCH v6 14/30] riscv: hart: Extract hart realize to a separate routine, Bin Meng, 2019/08/27
- [Qemu-devel] [PATCH v6 22/30] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes, Bin Meng, 2019/08/27
- [Qemu-devel] [PATCH v6 16/30] riscv: sifive_u: Set the minimum number of cpus to 2, Bin Meng, 2019/08/27
- [Qemu-devel] [PATCH v6 18/30] riscv: sifive_u: Update PLIC hart topology configuration string, Bin Meng, 2019/08/27
- [Qemu-devel] [PATCH v6 20/30] riscv: sifive_u: Generate hfclk and rtcclk nodes, Bin Meng, 2019/08/27
- [Qemu-devel] [PATCH v6 15/30] riscv: hart: Add a "hartid-base" property to RISC-V hart array, Bin Meng, 2019/08/27
- Re: [Qemu-devel] [PATCH v6 15/30] riscv: hart: Add a "hartid-base" property to RISC-V hart array,
Alistair Francis <=
- [Qemu-devel] [PATCH v6 21/30] riscv: sifive_u: Add PRCI block to the SoC, Bin Meng, 2019/08/27
- [Qemu-devel] [PATCH v6 27/30] riscv: sifive_u: Instantiate OTP memory with a serial number, Bin Meng, 2019/08/27
- [Qemu-devel] [PATCH v6 23/30] riscv: sifive_u: Update UART base addresses and IRQs, Bin Meng, 2019/08/27
- [Qemu-devel] [PATCH v6 30/30] riscv: sifive_u: Update model and compatible strings in device tree, Bin Meng, 2019/08/27
- [Qemu-devel] [PATCH v6 29/30] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet, Bin Meng, 2019/08/27
- [Qemu-devel] [PATCH v6 28/30] riscv: sifive_u: Fix broken GEM support, Bin Meng, 2019/08/27
- [Qemu-devel] [PATCH v6 19/30] riscv: sifive: Implement PRCI model for FU540, Bin Meng, 2019/08/27
- [Qemu-devel] [PATCH v6 17/30] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC, Bin Meng, 2019/08/27
- [Qemu-devel] [PATCH v6 26/30] riscv: sifive: Implement a model for SiFive FU540 OTP, Bin Meng, 2019/08/27
- [Qemu-devel] [PATCH v6 25/30] riscv: roms: Update default bios for sifive_u machine, Bin Meng, 2019/08/27