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[Qemu-devel] [PULL 01/31] target/mips: Clean up handling of CP0 register
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PULL 01/31] target/mips: Clean up handling of CP0 register 0 |
Date: |
Thu, 29 Aug 2019 12:24:43 +0200 |
From: Aleksandar Markovic <address@hidden>
Clean up handling of CP0 register 0.
Reviewed-by: Aleksandar Rikalo <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
Message-Id: <address@hidden>
---
target/mips/cpu.h | 3 +++
target/mips/translate.c | 40 ++++++++++++++++++++--------------------
2 files changed, 23 insertions(+), 20 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 1fd4a18..42d0e44 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -277,6 +277,9 @@ typedef struct mips_def_t mips_def_t;
/* CP0 Register 00 */
#define CP0_REG00__INDEX 0
+#define CP0_REG00__MVPCONTROL 1
+#define CP0_REG00__MVPCONF0 2
+#define CP0_REG00__MVPCONF1 3
#define CP0_REG00__VPCONTROL 4
/* CP0 Register 01 */
/* CP0 Register 02 */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 8ebde6f..c3fcfb4 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -6813,26 +6813,26 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
switch (reg) {
case CP0_REGISTER_00:
switch (sel) {
- case 0:
+ case CP0_REG00__INDEX:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Index));
register_name = "Index";
break;
- case 1:
+ case CP0_REG00__MVPCONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_mvpcontrol(arg, cpu_env);
register_name = "MVPControl";
break;
- case 2:
+ case CP0_REG00__MVPCONF0:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_mvpconf0(arg, cpu_env);
register_name = "MVPConf0";
break;
- case 3:
+ case CP0_REG00__MVPCONF1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_mvpconf1(arg, cpu_env);
register_name = "MVPConf1";
break;
- case 4:
+ case CP0_REG00__VPCONTROL:
CP0_CHECK(ctx->vp);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPControl));
register_name = "VPControl";
@@ -7573,26 +7573,26 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
switch (reg) {
case CP0_REGISTER_00:
switch (sel) {
- case 0:
+ case CP0_REG00__INDEX:
gen_helper_mtc0_index(cpu_env, arg);
register_name = "Index";
break;
- case 1:
+ case CP0_REG00__MVPCONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_mvpcontrol(cpu_env, arg);
register_name = "MVPControl";
break;
- case 2:
+ case CP0_REG00__MVPCONF0:
CP0_CHECK(ctx->insn_flags & ASE_MT);
/* ignored */
register_name = "MVPConf0";
break;
- case 3:
+ case CP0_REG00__MVPCONF1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
/* ignored */
register_name = "MVPConf1";
break;
- case 4:
+ case CP0_REG00__VPCONTROL:
CP0_CHECK(ctx->vp);
/* ignored */
register_name = "VPControl";
@@ -8319,26 +8319,26 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
switch (reg) {
case CP0_REGISTER_00:
switch (sel) {
- case 0:
+ case CP0_REG00__INDEX:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Index));
register_name = "Index";
break;
- case 1:
+ case CP0_REG00__MVPCONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_mvpcontrol(arg, cpu_env);
register_name = "MVPControl";
break;
- case 2:
+ case CP0_REG00__MVPCONF0:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_mvpconf0(arg, cpu_env);
register_name = "MVPConf0";
break;
- case 3:
+ case CP0_REG00__MVPCONF1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_mvpconf1(arg, cpu_env);
register_name = "MVPConf1";
break;
- case 4:
+ case CP0_REG00__VPCONTROL:
CP0_CHECK(ctx->vp);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPControl));
register_name = "VPControl";
@@ -9033,26 +9033,26 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
switch (reg) {
case CP0_REGISTER_00:
switch (sel) {
- case 0:
+ case CP0_REG00__INDEX:
gen_helper_mtc0_index(cpu_env, arg);
register_name = "Index";
break;
- case 1:
+ case CP0_REG00__MVPCONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_mvpcontrol(cpu_env, arg);
register_name = "MVPControl";
break;
- case 2:
+ case CP0_REG00__MVPCONF0:
CP0_CHECK(ctx->insn_flags & ASE_MT);
/* ignored */
register_name = "MVPConf0";
break;
- case 3:
+ case CP0_REG00__MVPCONF1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
/* ignored */
register_name = "MVPConf1";
break;
- case 4:
+ case CP0_REG00__VPCONTROL:
CP0_CHECK(ctx->vp);
/* ignored */
register_name = "VPControl";
--
2.7.4
- [Qemu-devel] [PULL 00/31] MIPS queue for August 29th, 2019, Aleksandar Markovic, 2019/08/29
- [Qemu-devel] [PULL 01/31] target/mips: Clean up handling of CP0 register 0,
Aleksandar Markovic <=
- [Qemu-devel] [PULL 02/31] target/mips: Clean up handling of CP0 register 1, Aleksandar Markovic, 2019/08/29
- [Qemu-devel] [PULL 05/31] target/mips: Clean up handling of CP0 register 4, Aleksandar Markovic, 2019/08/29
- [Qemu-devel] [PULL 08/31] target/mips: Clean up handling of CP0 register 7, Aleksandar Markovic, 2019/08/29
- [Qemu-devel] [PULL 03/31] target/mips: Clean up handling of CP0 register 2, Aleksandar Markovic, 2019/08/29
- [Qemu-devel] [PULL 10/31] target/mips: Clean up handling of CP0 register 9, Aleksandar Markovic, 2019/08/29
- [Qemu-devel] [PULL 15/31] target/mips: Clean up handling of CP0 register 14, Aleksandar Markovic, 2019/08/29
- [Qemu-devel] [PULL 06/31] target/mips: Clean up handling of CP0 register 5, Aleksandar Markovic, 2019/08/29
- [Qemu-devel] [PULL 07/31] target/mips: Clean up handling of CP0 register 6, Aleksandar Markovic, 2019/08/29
- [Qemu-devel] [PULL 24/31] target/mips: Clean up handling of CP0 register 25, Aleksandar Markovic, 2019/08/29
- [Qemu-devel] [PULL 12/31] target/mips: Clean up handling of CP0 register 11, Aleksandar Markovic, 2019/08/29