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[Qemu-devel] [PATCH v3 30/69] target/arm: Diagnose too few registers in
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v3 30/69] target/arm: Diagnose too few registers in list for LDM/STM |
Date: |
Wed, 28 Aug 2019 12:04:17 -0700 |
This has been a TODO item for quite a while. The minimum bit
count for A32 and T16 is 1, and for T32 is 2.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/translate.c | 26 ++++++++++++++++++--------
1 file changed, 18 insertions(+), 8 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 529660eb35..bfc4508321 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9813,7 +9813,7 @@ static void op_addr_block_post(DisasContext *s,
arg_ldst_block *a,
}
}
-static bool op_stm(DisasContext *s, arg_ldst_block *a)
+static bool op_stm(DisasContext *s, arg_ldst_block *a, int min_n)
{
int i, j, n, list, mem_idx;
bool user = a->u;
@@ -9830,7 +9830,10 @@ static bool op_stm(DisasContext *s, arg_ldst_block *a)
list = a->list;
n = ctpop16(list);
- /* TODO: test invalid n == 0 case */
+ if (n < min_n) {
+ unallocated_encoding(s);
+ return true;
+ }
addr = op_addr_block_pre(s, a, n);
mem_idx = get_mem_index(s);
@@ -9863,7 +9866,8 @@ static bool op_stm(DisasContext *s, arg_ldst_block *a)
static bool trans_STM(DisasContext *s, arg_ldst_block *a)
{
- return op_stm(s, a);
+ /* BitCount(list) < 1 is UNPREDICTABLE */
+ return op_stm(s, a, 1);
}
static bool trans_STM_t32(DisasContext *s, arg_ldst_block *a)
@@ -9873,10 +9877,11 @@ static bool trans_STM_t32(DisasContext *s,
arg_ldst_block *a)
unallocated_encoding(s);
return true;
}
- return op_stm(s, a);
+ /* BitCount(list) < 2 is UNPREDICTABLE */
+ return op_stm(s, a, 2);
}
-static bool do_ldm(DisasContext *s, arg_ldst_block *a)
+static bool do_ldm(DisasContext *s, arg_ldst_block *a, int min_n)
{
int i, j, n, list, mem_idx;
bool loaded_base;
@@ -9905,7 +9910,10 @@ static bool do_ldm(DisasContext *s, arg_ldst_block *a)
list = a->list;
n = ctpop16(list);
- /* TODO: test invalid n == 0 case */
+ if (n < min_n) {
+ unallocated_encoding(s);
+ return true;
+ }
addr = op_addr_block_pre(s, a, n);
mem_idx = get_mem_index(s);
@@ -9973,7 +9981,8 @@ static bool trans_LDM_a32(DisasContext *s, arg_ldst_block
*a)
unallocated_encoding(s);
return true;
}
- return do_ldm(s, a);
+ /* BitCount(list) < 1 is UNPREDICTABLE */
+ return do_ldm(s, a, 1);
}
static bool trans_LDM_t32(DisasContext *s, arg_ldst_block *a)
@@ -9983,7 +9992,8 @@ static bool trans_LDM_t32(DisasContext *s, arg_ldst_block
*a)
unallocated_encoding(s);
return true;
}
- return do_ldm(s, a);
+ /* BitCount(list) < 2 is UNPREDICTABLE */
+ return do_ldm(s, a, 2);
}
/*
--
2.17.1
- [Qemu-devel] [PATCH v3 23/69] target/arm: Convert USAD8, USADA8, SBFX, UBFX, BFC, BFI, UDF, (continued)
- [Qemu-devel] [PATCH v3 23/69] target/arm: Convert USAD8, USADA8, SBFX, UBFX, BFC, BFI, UDF, Richard Henderson, 2019/08/28
- [Qemu-devel] [PATCH v3 21/69] target/arm: Convert Synchronization primitives, Richard Henderson, 2019/08/28
- [Qemu-devel] [PATCH v3 24/69] target/arm: Convert Parallel addition and subtraction, Richard Henderson, 2019/08/28
- [Qemu-devel] [PATCH v3 27/69] target/arm: Convert MOVW, MOVT, Richard Henderson, 2019/08/28
- [Qemu-devel] [PATCH v3 29/69] target/arm: Diagnose writeback register in list for LDM for v7, Richard Henderson, 2019/08/28
- [Qemu-devel] [PATCH v3 25/69] target/arm: Convert packing, unpacking, saturation, and reversal, Richard Henderson, 2019/08/28
- [Qemu-devel] [PATCH v3 20/69] target/arm: Convert load/store (register, immediate, literal), Richard Henderson, 2019/08/28
- [Qemu-devel] [PATCH v3 31/69] target/arm: Diagnose base == pc for LDM/STM, Richard Henderson, 2019/08/28
- [Qemu-devel] [PATCH v3 26/69] target/arm: Convert Signed multiply, signed and unsigned divide, Richard Henderson, 2019/08/28
- [Qemu-devel] [PATCH v3 32/69] target/arm: Convert B, BL, BLX (immediate), Richard Henderson, 2019/08/28
- [Qemu-devel] [PATCH v3 30/69] target/arm: Diagnose too few registers in list for LDM/STM,
Richard Henderson <=
- [Qemu-devel] [PATCH v3 40/69] target/arm: Convert Table Branch, Richard Henderson, 2019/08/28
- [Qemu-devel] [PATCH v3 36/69] target/arm: Convert CPS (privileged), Richard Henderson, 2019/08/28
- [Qemu-devel] [PATCH v3 37/69] target/arm: Convert SETEND, Richard Henderson, 2019/08/28
- [Qemu-devel] [PATCH v3 38/69] target/arm: Convert PLI, PLD, PLDW, Richard Henderson, 2019/08/28
- [Qemu-devel] [PATCH v3 34/69] target/arm: Convert RFE and SRS, Richard Henderson, 2019/08/28
- [Qemu-devel] [PATCH v3 42/69] target/arm: Convert TT, Richard Henderson, 2019/08/28
- [Qemu-devel] [PATCH v3 44/69] target/arm: Simplify disas_arm_insn, Richard Henderson, 2019/08/28
- [Qemu-devel] [PATCH v3 47/69] target/arm: Convert T16 load/store (register offset), Richard Henderson, 2019/08/28
- [Qemu-devel] [PATCH v3 50/69] target/arm: Convert T16 load/store multiple, Richard Henderson, 2019/08/28
- [Qemu-devel] [PATCH v3 41/69] target/arm: Convert SG, Richard Henderson, 2019/08/28