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Re: [Qemu-devel] [PATCH v2 42/68] target/arm: Simplify disas_thumb2_insn
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From: |
Peter Maydell |
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Subject: |
Re: [Qemu-devel] [PATCH v2 42/68] target/arm: Simplify disas_thumb2_insn |
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Date: |
Sun, 25 Aug 2019 17:35:15 +0100 |
On Mon, 19 Aug 2019 at 22:38, Richard Henderson
<address@hidden> wrote:
>
> Fold away all of the cases that now just goto illegal_op,
> because all of their internal bits are now in decodetree.
>
> Signed-off-by: Richard Henderson <address@hidden>
> ---
Reviewed-by: Peter Maydell <address@hidden>
thanks
-- PMM
- Re: [Qemu-devel] [PATCH v2 38/68] target/arm: Convert Unallocated memory hint, (continued)
- [Qemu-devel] [PATCH v2 41/68] target/arm: Convert TT, Richard Henderson, 2019/08/19
- [Qemu-devel] [PATCH v2 39/68] target/arm: Convert Table Branch, Richard Henderson, 2019/08/19
- [Qemu-devel] [PATCH v2 40/68] target/arm: Convert SG, Richard Henderson, 2019/08/19
- [Qemu-devel] [PATCH v2 44/68] target/arm: Add skeleton for T16 decodetree, Richard Henderson, 2019/08/19
- [Qemu-devel] [PATCH v2 42/68] target/arm: Simplify disas_thumb2_insn, Richard Henderson, 2019/08/19
- Re: [Qemu-devel] [PATCH v2 42/68] target/arm: Simplify disas_thumb2_insn,
Peter Maydell <=
- [Qemu-devel] [PATCH v2 45/68] target/arm: Convert T16 data-processing (two low regs), Richard Henderson, 2019/08/19
- [Qemu-devel] [PATCH v2 46/68] target/arm: Convert T16 load/store (register offset), Richard Henderson, 2019/08/19
- [Qemu-devel] [PATCH v2 43/68] target/arm: Simplify disas_arm_insn, Richard Henderson, 2019/08/19
- [Qemu-devel] [PATCH v2 51/68] target/arm: Convert T16 one low register and immediate, Richard Henderson, 2019/08/19
- [Qemu-devel] [PATCH v2 52/68] target/arm: Convert T16 branch and exchange, Richard Henderson, 2019/08/19