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[Qemu-devel] [PATCH v5 07/30] riscv: roms: Remove executable attribute o
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From: |
Bin Meng |
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Subject: |
[Qemu-devel] [PATCH v5 07/30] riscv: roms: Remove executable attribute of opensbi images |
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Date: |
Thu, 22 Aug 2019 22:10:46 -0700 |
Like other binary files, the executable attribute of opensbi images
should not be set.
Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
---
Changes in v5: None
Changes in v4:
- new patch to remove executable attribute of opensbi images
Changes in v3: None
Changes in v2: None
pc-bios/opensbi-riscv32-virt-fw_jump.bin | Bin
pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin | Bin
pc-bios/opensbi-riscv64-virt-fw_jump.bin | Bin
3 files changed, 0 insertions(+), 0 deletions(-)
mode change 100755 => 100644 pc-bios/opensbi-riscv32-virt-fw_jump.bin
mode change 100755 => 100644 pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin
mode change 100755 => 100644 pc-bios/opensbi-riscv64-virt-fw_jump.bin
diff --git a/pc-bios/opensbi-riscv32-virt-fw_jump.bin
b/pc-bios/opensbi-riscv32-virt-fw_jump.bin
old mode 100755
new mode 100644
diff --git a/pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin
b/pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin
old mode 100755
new mode 100644
diff --git a/pc-bios/opensbi-riscv64-virt-fw_jump.bin
b/pc-bios/opensbi-riscv64-virt-fw_jump.bin
old mode 100755
new mode 100644
--
2.7.4
- [Qemu-devel] [PATCH v5 00/30] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine, Bin Meng, 2019/08/23
- [Qemu-devel] [PATCH v5 01/30] riscv: hw: Remove superfluous "linux, phandle" property, Bin Meng, 2019/08/23
- [Qemu-devel] [PATCH v5 03/30] riscv: hw: Remove not needed PLIC properties in device tree, Bin Meng, 2019/08/23
- [Qemu-devel] [PATCH v5 04/30] riscv: hw: Change create_fdt() to return void, Bin Meng, 2019/08/23
- [Qemu-devel] [PATCH v5 02/30] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell, Bin Meng, 2019/08/23
- [Qemu-devel] [PATCH v5 05/30] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead, Bin Meng, 2019/08/23
- [Qemu-devel] [PATCH v5 06/30] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h, Bin Meng, 2019/08/23
- [Qemu-devel] [PATCH v5 07/30] riscv: roms: Remove executable attribute of opensbi images,
Bin Meng <=
- [Qemu-devel] [PATCH v5 10/30] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming, Bin Meng, 2019/08/23
- [Qemu-devel] [PATCH v5 08/30] riscv: sifive_u: Remove the unnecessary include of prci header, Bin Meng, 2019/08/23
- [Qemu-devel] [PATCH v5 09/30] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}, Bin Meng, 2019/08/23
- [Qemu-devel] [PATCH v5 11/30] riscv: sifive_e: prci: Update the PRCI register block size, Bin Meng, 2019/08/23
- [Qemu-devel] [PATCH v5 13/30] riscv: Add a sifive_cpu.h to include both E and U cpu type defines, Bin Meng, 2019/08/23
- [Qemu-devel] [PATCH v5 14/30] riscv: hart: Extract hart realize to a separate routine, Bin Meng, 2019/08/23
- [Qemu-devel] [PATCH v5 15/30] riscv: hart: Add a "hartid-base" property to RISC-V hart array, Bin Meng, 2019/08/23
- [Qemu-devel] [PATCH v5 17/30] riscv: sifive_u: Set the minimum number of cpus to 2, Bin Meng, 2019/08/23