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[Qemu-devel] [PATCH 02/26] target/mips: Clean up handling of CP0 registe
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From: |
Aleksandar Markovic |
|
Subject: |
[Qemu-devel] [PATCH 02/26] target/mips: Clean up handling of CP0 register 1 |
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Date: |
Thu, 22 Aug 2019 13:35:26 +0200 |
From: Aleksandar Markovic <address@hidden>
Clean up handling of CP0 register 1.
Signed-off-by: Aleksandar Markovic <address@hidden>
---
target/mips/cpu.h | 8 +++++++
target/mips/translate.c | 64 ++++++++++++++++++++++++-------------------------
2 files changed, 40 insertions(+), 32 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index e2f6844..597afa8 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -284,6 +284,14 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG00__MVPCONF1 3
#define CP0_REG00__VPCONTROL 4
/* CP0 Register 01 */
+#define CP0_REG01__RANDOM 0
+#define CP0_REG01__VPECONTROL 1
+#define CP0_REG01__VPECONF0 2
+#define CP0_REG01__VPECONF1 3
+#define CP0_REG01__YQMASK 4
+#define CP0_REG01__VPESCHEDULE 5
+#define CP0_REG01__VPESCHEFBACK 6
+#define CP0_REG01__VPEOPT 7
/* CP0 Register 02 */
#define CP0_REG02__ENTRYLO0 0
/* CP0 Register 03 */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 06a1646..e350545 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -6883,42 +6883,42 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_01:
switch (sel) {
- case 0:
+ case CP0_REG01__RANDOM:
CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6));
gen_helper_mfc0_random(arg, cpu_env);
register_name = "Random";
break;
- case 1:
+ case CP0_REG01__VPECONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEControl));
register_name = "VPEControl";
break;
- case 2:
+ case CP0_REG01__VPECONF0:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf0));
register_name = "VPEConf0";
break;
- case 3:
+ case CP0_REG01__VPECONF1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf1));
register_name = "VPEConf1";
break;
- case 4:
+ case CP0_REG01__YQMASK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_YQMask));
register_name = "YQMask";
break;
- case 5:
+ case CP0_REG01__VPESCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_VPESchedule));
register_name = "VPESchedule";
break;
- case 6:
+ case CP0_REG01__VPESCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_VPEScheFBack));
register_name = "VPEScheFBack";
break;
- case 7:
+ case CP0_REG01__VPEOPT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEOpt));
register_name = "VPEOpt";
@@ -7651,43 +7651,43 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_01:
switch (sel) {
- case 0:
+ case CP0_REG01__RANDOM:
/* ignored */
register_name = "Random";
break;
- case 1:
+ case CP0_REG01__VPECONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_vpecontrol(cpu_env, arg);
register_name = "VPEControl";
break;
- case 2:
+ case CP0_REG01__VPECONF0:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_vpeconf0(cpu_env, arg);
register_name = "VPEConf0";
break;
- case 3:
+ case CP0_REG01__VPECONF1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_vpeconf1(cpu_env, arg);
register_name = "VPEConf1";
break;
- case 4:
+ case CP0_REG01__YQMASK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_yqmask(cpu_env, arg);
register_name = "YQMask";
break;
- case 5:
+ case CP0_REG01__VPESCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
tcg_gen_st_tl(arg, cpu_env,
offsetof(CPUMIPSState, CP0_VPESchedule));
register_name = "VPESchedule";
break;
- case 6:
+ case CP0_REG01__VPESCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
tcg_gen_st_tl(arg, cpu_env,
offsetof(CPUMIPSState, CP0_VPEScheFBack));
register_name = "VPEScheFBack";
break;
- case 7:
+ case CP0_REG01__VPEOPT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_vpeopt(cpu_env, arg);
register_name = "VPEOpt";
@@ -8403,42 +8403,42 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_01:
switch (sel) {
- case 0:
+ case CP0_REG01__RANDOM:
CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6));
gen_helper_mfc0_random(arg, cpu_env);
register_name = "Random";
break;
- case 1:
+ case CP0_REG01__VPECONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEControl));
register_name = "VPEControl";
break;
- case 2:
+ case CP0_REG01__VPECONF0:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf0));
register_name = "VPEConf0";
break;
- case 3:
+ case CP0_REG01__VPECONF1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf1));
register_name = "VPEConf1";
break;
- case 4:
+ case CP0_REG01__YQMASK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_YQMask));
register_name = "YQMask";
break;
- case 5:
+ case CP0_REG01__VPESCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState,
CP0_VPESchedule));
register_name = "VPESchedule";
break;
- case 6:
+ case CP0_REG01__VPESCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState,
CP0_VPEScheFBack));
register_name = "VPEScheFBack";
break;
- case 7:
+ case CP0_REG01__VPEOPT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEOpt));
register_name = "VPEOpt";
@@ -9125,41 +9125,41 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int
reg, int sel)
break;
case CP0_REGISTER_01:
switch (sel) {
- case 0:
+ case CP0_REG01__RANDOM:
/* ignored */
register_name = "Random";
break;
- case 1:
+ case CP0_REG01__VPECONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_vpecontrol(cpu_env, arg);
register_name = "VPEControl";
break;
- case 2:
+ case CP0_REG01__VPECONF0:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_vpeconf0(cpu_env, arg);
register_name = "VPEConf0";
break;
- case 3:
+ case CP0_REG01__VPECONF1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_vpeconf1(cpu_env, arg);
register_name = "VPEConf1";
break;
- case 4:
+ case CP0_REG01__YQMASK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_yqmask(cpu_env, arg);
register_name = "YQMask";
break;
- case 5:
+ case CP0_REG01__VPESCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState,
CP0_VPESchedule));
register_name = "VPESchedule";
break;
- case 6:
+ case CP0_REG01__VPESCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState,
CP0_VPEScheFBack));
register_name = "VPEScheFBack";
break;
- case 7:
+ case CP0_REG01__VPEOPT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_vpeopt(cpu_env, arg);
register_name = "VPEOpt";
--
2.7.4
- [Qemu-devel] [PATCH 00/26] Clean up handling of configuration register CP0, Aleksandar Markovic, 2019/08/22
- [Qemu-devel] [PATCH 10/26] target/mips: Clean up handling of CP0 register 11, Aleksandar Markovic, 2019/08/22
- [Qemu-devel] [PATCH 09/26] target/mips: Clean up handling of CP0 register 10, Aleksandar Markovic, 2019/08/22
- [Qemu-devel] [PATCH 01/26] target/mips: Clean up handling of CP0 register 0, Aleksandar Markovic, 2019/08/22
- [Qemu-devel] [PATCH 07/26] target/mips: Clean up handling of CP0 register 8, Aleksandar Markovic, 2019/08/22
- [Qemu-devel] [PATCH 04/26] target/mips: Clean up handling of CP0 register 5, Aleksandar Markovic, 2019/08/22
- [Qemu-devel] [PATCH 02/26] target/mips: Clean up handling of CP0 register 1,
Aleksandar Markovic <=
- [Qemu-devel] [PATCH 06/26] target/mips: Clean up handling of CP0 register 7, Aleksandar Markovic, 2019/08/22
- [Qemu-devel] [PATCH 08/26] target/mips: Clean up handling of CP0 register 9, Aleksandar Markovic, 2019/08/22
- [Qemu-devel] [PATCH 16/26] target/mips: Clean up handling of CP0 register 19, Aleksandar Markovic, 2019/08/22
- [Qemu-devel] [PATCH 14/26] target/mips: Clean up handling of CP0 register 17, Aleksandar Markovic, 2019/08/22
- [Qemu-devel] [PATCH 13/26] target/mips: Clean up handling of CP0 register 16, Aleksandar Markovic, 2019/08/22
- [Qemu-devel] [PATCH 12/26] target/mips: Clean up handling of CP0 register 15, Aleksandar Markovic, 2019/08/22
- [Qemu-devel] [PATCH 03/26] target/mips: Clean up handling of CP0 register 2, Aleksandar Markovic, 2019/08/22
- [Qemu-devel] [PATCH 15/26] target/mips: Clean up handling of CP0 register 18, Aleksandar Markovic, 2019/08/22
- [Qemu-devel] [PATCH 11/26] target/mips: Clean up handling of CP0 register 12, Aleksandar Markovic, 2019/08/22
- [Qemu-devel] [PATCH 05/26] target/mips: Clean up handling of CP0 register 6, Aleksandar Markovic, 2019/08/22