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[Qemu-devel] [RFC PATCH v4 47/75] target/i386: introduce SSE3 vector ins
From: |
Jan Bobek |
Subject: |
[Qemu-devel] [RFC PATCH v4 47/75] target/i386: introduce SSE3 vector instructions to sse-opcode.inc.h |
Date: |
Wed, 21 Aug 2019 13:29:23 -0400 |
Add all the SSE3 vector instruction entries to sse-opcode.inc.h.
Signed-off-by: Jan Bobek <address@hidden>
---
target/i386/sse-opcode.inc.h | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/target/i386/sse-opcode.inc.h b/target/i386/sse-opcode.inc.h
index 6df5fda010..84785a4e04 100644
--- a/target/i386/sse-opcode.inc.h
+++ b/target/i386/sse-opcode.inc.h
@@ -341,6 +341,19 @@
* NP 0F AE /7 CLFLUSH m8
* NP 0F AE /5 LFENCE
* NP 0F AE /6 MFENCE
+ *
+ * SSE3 Instructions
+ * ------------------
+ * F2 0F F0 /r LDDQU xmm1, m128
+ * F3 0F 16 /r MOVSHDUP xmm1, xmm2/m128
+ * F3 0F 12 /r MOVSLDUP xmm1, xmm2/m128
+ * F2 0F 12 /r MOVDDUP xmm1, xmm2/m64
+ * F2 0F 7C /r HADDPS xmm1, xmm2/m128
+ * 66 0F 7C /r HADDPD xmm1, xmm2/m128
+ * F2 0F 7D /r HSUBPS xmm1, xmm2/m128
+ * 66 0F 7D /r HSUBPD xmm1, xmm2/m128
+ * F2 0F D0 /r ADDSUBPS xmm1, xmm2/m128
+ * 66 0F D0 /r ADDSUBPD xmm1, xmm2/m128
*/
OPCODE(movd, LEG(NP, 0F, 0, 0x6e), MMX, WR, Pq, Ed)
@@ -389,6 +402,10 @@ OPCODE(movmskps, LEG(NP, 0F, 0, 0x50), SSE, WR, Gd, Udq)
OPCODE(movmskps, LEG(NP, 0F, 1, 0x50), SSE, WR, Gq, Udq)
OPCODE(movmskpd, LEG(66, 0F, 0, 0x50), SSE2, WR, Gd, Udq)
OPCODE(movmskpd, LEG(66, 0F, 1, 0x50), SSE2, WR, Gq, Udq)
+OPCODE(lddqu, LEG(F2, 0F, 0, 0xf0), SSE3, WR, Vdq, Mdq)
+OPCODE(movshdup, LEG(F3, 0F, 0, 0x16), SSE3, WR, Vdq, Wdq)
+OPCODE(movsldup, LEG(F3, 0F, 0, 0x12), SSE3, WR, Vdq, Wdq)
+OPCODE(movddup, LEG(F2, 0F, 0, 0x12), SSE3, WR, Vdq, Wq)
OPCODE(paddb, LEG(NP, 0F, 0, 0xfc), MMX, WRR, Pq, Pq, Qq)
OPCODE(paddb, LEG(66, 0F, 0, 0xfc), SSE2, WRR, Vdq, Vdq, Wdq)
OPCODE(paddw, LEG(NP, 0F, 0, 0xfd), MMX, WRR, Pq, Pq, Qq)
@@ -409,6 +426,8 @@ OPCODE(addps, LEG(NP, 0F, 0, 0x58), SSE, WRR, Vdq, Vdq, Wdq)
OPCODE(addpd, LEG(66, 0F, 0, 0x58), SSE2, WRR, Vdq, Vdq, Wdq)
OPCODE(addss, LEG(F3, 0F, 0, 0x58), SSE, WRR, Vd, Vd, Wd)
OPCODE(addsd, LEG(F2, 0F, 0, 0x58), SSE2, WRR, Vq, Vq, Wq)
+OPCODE(haddps, LEG(F2, 0F, 0, 0x7c), SSE3, WRR, Vdq, Vdq, Wdq)
+OPCODE(haddpd, LEG(66, 0F, 0, 0x7c), SSE3, WRR, Vdq, Vdq, Wdq)
OPCODE(psubb, LEG(NP, 0F, 0, 0xf8), MMX, WRR, Pq, Pq, Qq)
OPCODE(psubb, LEG(66, 0F, 0, 0xf8), SSE2, WRR, Vdq, Vdq, Wdq)
OPCODE(psubw, LEG(NP, 0F, 0, 0xf9), MMX, WRR, Pq, Pq, Qq)
@@ -429,6 +448,10 @@ OPCODE(subps, LEG(NP, 0F, 0, 0x5c), SSE, WRR, Vdq, Vdq,
Wdq)
OPCODE(subpd, LEG(66, 0F, 0, 0x5c), SSE2, WRR, Vdq, Vdq, Wdq)
OPCODE(subss, LEG(F3, 0F, 0, 0x5c), SSE, WRR, Vd, Vd, Wd)
OPCODE(subsd, LEG(F2, 0F, 0, 0x5c), SSE2, WRR, Vq, Vq, Wq)
+OPCODE(hsubps, LEG(F2, 0F, 0, 0x7d), SSE3, WRR, Vdq, Vdq, Wdq)
+OPCODE(hsubpd, LEG(66, 0F, 0, 0x7d), SSE3, WRR, Vdq, Vdq, Wdq)
+OPCODE(addsubps, LEG(F2, 0F, 0, 0xd0), SSE3, WRR, Vdq, Vdq, Wdq)
+OPCODE(addsubpd, LEG(66, 0F, 0, 0xd0), SSE3, WRR, Vdq, Vdq, Wdq)
OPCODE(pmullw, LEG(NP, 0F, 0, 0xd5), MMX, WRR, Pq, Pq, Qq)
OPCODE(pmullw, LEG(66, 0F, 0, 0xd5), SSE2, WRR, Vdq, Vdq, Wdq)
OPCODE(pmulhw, LEG(NP, 0F, 0, 0xe5), MMX, WRR, Pq, Pq, Qq)
--
2.20.1
- [Qemu-devel] [RFC PATCH v4 40/75] target/i386: introduce SSE code generators, (continued)
- [Qemu-devel] [RFC PATCH v4 40/75] target/i386: introduce SSE code generators, Jan Bobek, 2019/08/21
- [Qemu-devel] [RFC PATCH v4 42/75] target/i386: introduce SSE2 translators, Jan Bobek, 2019/08/21
- [Qemu-devel] [RFC PATCH v4 54/75] target/i386: introduce SSE4.2 code generators, Jan Bobek, 2019/08/21
- [Qemu-devel] [RFC PATCH v4 46/75] target/i386: introduce SSE3 code generators, Jan Bobek, 2019/08/21
- [Qemu-devel] [RFC PATCH v4 52/75] target/i386: introduce SSE4.1 code generators, Jan Bobek, 2019/08/21
- [Qemu-devel] [RFC PATCH v4 48/75] target/i386: introduce SSSE3 translators, Jan Bobek, 2019/08/21
- [Qemu-devel] [RFC PATCH v4 44/75] target/i386: introduce SSE2 vector instructions to sse-opcode.inc.h, Jan Bobek, 2019/08/21
- [Qemu-devel] [RFC PATCH v4 62/75] target/i386: introduce AVX2 translators, Jan Bobek, 2019/08/21
- [Qemu-devel] [RFC PATCH v4 53/75] target/i386: introduce SSE4.1 vector instructions to sse-opcode.inc.h, Jan Bobek, 2019/08/21
- [Qemu-devel] [RFC PATCH v4 59/75] target/i386: introduce AVX translators, Jan Bobek, 2019/08/21
- [Qemu-devel] [RFC PATCH v4 47/75] target/i386: introduce SSE3 vector instructions to sse-opcode.inc.h,
Jan Bobek <=
- [Qemu-devel] [RFC PATCH v4 51/75] target/i386: introduce SSE4.1 translators, Jan Bobek, 2019/08/21
- [Qemu-devel] [RFC PATCH v4 66/75] target/i386: cleanup leftovers in ops_sse_header.h, Jan Bobek, 2019/08/21
- [Qemu-devel] [RFC PATCH v4 67/75] target/i386: introduce aliases for helper-based tcg_gen_gvec_* functions, Jan Bobek, 2019/08/21
- [Qemu-devel] [RFC PATCH v4 69/75] target/i386: convert pmullw/pmulhw/pmulhuw helpers to gvec style, Jan Bobek, 2019/08/21
- [Qemu-devel] [RFC PATCH v4 43/75] target/i386: introduce SSE2 code generators, Jan Bobek, 2019/08/21
- [Qemu-devel] [RFC PATCH v4 50/75] target/i386: introduce SSSE3 vector instructions to sse-opcode.inc.h, Jan Bobek, 2019/08/21
- [Qemu-devel] [RFC PATCH v4 55/75] target/i386: introduce SSE4.2 vector instructions to sse-opcode.inc.h, Jan Bobek, 2019/08/21
- [Qemu-devel] [RFC PATCH v4 57/75] target/i386: introduce AES and PCLMULQDQ code generators, Jan Bobek, 2019/08/21
- [Qemu-devel] [RFC PATCH v4 58/75] target/i386: introduce AES and PCLMULQDQ vector instructions to sse-opcode.inc.h, Jan Bobek, 2019/08/21