[Qemu-devel] [RFC PATCH v4 00/75] rewrite MMX/SSE*/AVX/AVX2 vector instruction translation

[Jan Bobek]

Here comes the next version of my patch series, this time v4; the
previous version can be found at [1].

This version can decode all vector instructions up to AVX2. However,
note that this does not mean all of these instructions are implemented
correctly: to achieve that, the old ad-hoc style helpers will need to
be rewritten into the style used by gvec helpers (initial effort
towards that goal can be seen in patches 65-75). There is also a
number of instructions which have not been previously implemented at
all, for which the helpers need to be written from scratch.

Cheers,
 -Jan

Changes from v3:
  - introduce disas_insn_prefix ([2])
  - rename ck_cpuid to check_cpuid ([3])
  - clarify this series deals with vector instructions only ([4])
  - add a list of instructions per each vector ISA extension ([5])
  - change return type of check_cpuid and insnop_init to bool ([6])

References:
  1. https://lists.nongnu.org/archive/html/qemu-devel/2019-08/msg02616.html
  2. https://lists.nongnu.org/archive/html/qemu-devel/2019-08/msg02686.html
  3. https://lists.nongnu.org/archive/html/qemu-devel/2019-08/msg04120.html
  4. https://lists.nongnu.org/archive/html/qemu-devel/2019-08/msg04119.html
  5. https://lists.nongnu.org/archive/html/qemu-devel/2019-08/msg02689.html
  6. https://lists.nongnu.org/archive/html/qemu-devel/2019-08/msg02701.html

Jan Bobek (72):
  target/i386: use dflag from DisasContext
  target/i386: use prefix from DisasContext
  target/i386: introduce disas_insn_prefix
  target/i386: use pc_start from DisasContext
  target/i386: make variable b1 const
  target/i386: make variable is_xmm const
  target/i386: add vector register file alignment constraints
  target/i386: introduce gen_sse_ng
  target/i386: introduce CASES_* macros in gen_sse_ng
  target/i386: decode the 0F38/0F3A prefix in gen_sse_ng
  target/i386: introduce aliases for some tcg_gvec operations
  target/i386: introduce function check_cpuid
  target/i386: disable AVX/AVX2 cpuid bitchecks
  target/i386: introduce instruction operand infrastructure
  target/i386: introduce generic operand alias
  target/i386: introduce generic either-or operand
  target/i386: introduce generic load-store operand
  target/i386: introduce tcg register operands
  target/i386: introduce modrm operand
  target/i386: introduce operands for decoding modrm fields
  target/i386: introduce operand for direct-only r/m field
  target/i386: introduce Ib (immediate) operand
  target/i386: introduce M* (memptr) operands
  target/i386: introduce G*, R*, E* (general register) operands
  target/i386: introduce P*, N*, Q* (MMX) operands
  target/i386: introduce H*, L*, V*, U*, W* (SSE/AVX) operands
  target/i386: alias H* operands with the V* operands
  target/i386: introduce code generators
  target/i386: introduce helper-based code generator macros
  target/i386: introduce gvec-based code generator macros
  target/i386: introduce sse-opcode.inc.h
  target/i386: introduce instruction translator macros
  target/i386: introduce MMX translators
  target/i386: introduce MMX code generators
  target/i386: introduce MMX vector instructions to sse-opcode.inc.h
  target/i386: introduce SSE translators
  target/i386: introduce SSE code generators
  target/i386: introduce SSE vector instructions to sse-opcode.inc.h
  target/i386: introduce SSE2 translators
  target/i386: introduce SSE2 code generators
  target/i386: introduce SSE2 vector instructions to sse-opcode.inc.h
  target/i386: introduce SSE3 translators
  target/i386: introduce SSE3 code generators
  target/i386: introduce SSE3 vector instructions to sse-opcode.inc.h
  target/i386: introduce SSSE3 translators
  target/i386: introduce SSSE3 code generators
  target/i386: introduce SSSE3 vector instructions to sse-opcode.inc.h
  target/i386: introduce SSE4.1 translators
  target/i386: introduce SSE4.1 code generators
  target/i386: introduce SSE4.1 vector instructions to sse-opcode.inc.h
  target/i386: introduce SSE4.2 code generators
  target/i386: introduce SSE4.2 vector instructions to sse-opcode.inc.h
  target/i386: introduce AES and PCLMULQDQ translators
  target/i386: introduce AES and PCLMULQDQ code generators
  target/i386: introduce AES and PCLMULQDQ vector instructions to
    sse-opcode.inc.h
  target/i386: introduce AVX translators
  target/i386: introduce AVX code generators
  target/i386: introduce AVX vector instructions to sse-opcode.inc.h
  target/i386: introduce AVX2 translators
  target/i386: introduce AVX2 code generators
  target/i386: introduce AVX2 vector instructions to sse-opcode.inc.h
  target/i386: remove obsoleted helpers
  target/i386: cleanup leftovers in ops_sse_header.h
  target/i386: introduce aliases for helper-based tcg_gen_gvec_*
    functions
  target/i386: convert ps((l,r)l(w,d,q),ra(w,d)) to helpers to gvec
    style
  target/i386: convert pmullw/pmulhw/pmulhuw helpers to gvec style
  target/i386: convert pavgb/pavgw helpers to gvec style
  target/i386: convert pmuludq/pmaddwd helpers to gvec style
  target/i386: convert psadbw helper to gvec style
  target/i386: remove obsoleted helper_mov(l,q)_mm_T0
  target/i386: convert pshuf(w,lw,hw,d),shuf(pd,ps) helpers to gvec
    style
  target/i386: convert pmovmskb/movmskps/movmskpd helpers to gvec style

Richard Henderson (3):
  target/i386: Push rex_r into DisasContext
  target/i386: Push rex_w into DisasContext
  target/i386: Simplify gen_exception arguments

 target/i386/cpu.h            |    6 +-
 target/i386/ops_sse.h        |  812 +++---
 target/i386/ops_sse_header.h |  131 +-
 target/i386/sse-opcode.inc.h | 2069 +++++++++++++++
 target/i386/translate.c      | 4777 ++++++++++++++++++++++++++++++----
 5 files changed, 6842 insertions(+), 953 deletions(-)
 create mode 100644 target/i386/sse-opcode.inc.h

-- 
2.20.1