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[Qemu-devel] [PATCH v3 5/7] target/riscv: Use both register name and ABI
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From: |
Alistair Francis |
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Subject: |
[Qemu-devel] [PATCH v3 5/7] target/riscv: Use both register name and ABI name |
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Date: |
Thu, 15 Aug 2019 14:34:58 -0700 |
From: Atish Patra <address@hidden>
Use both the generic register name and ABI name for the general purpose
registers and floating point registers.
Signed-off-by: Atish Patra <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
---
target/riscv/cpu.c | 19 +++++++++++--------
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f8d07bd20a..60b95daf60 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -33,17 +33,20 @@
static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG";
const char * const riscv_int_regnames[] = {
- "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2",
- "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5",
- "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7",
- "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6"
+ "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1",
+ "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3",
+ "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4",
+ "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11",
+ "x28/t3", "x29/t4", "x30/t5", "x31/t6"
};
const char * const riscv_fpr_regnames[] = {
- "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7",
- "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5",
- "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7",
- "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11"
+ "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5",
+ "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1",
+ "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7",
+ "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7",
+ "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9",
+ "f30/ft10", "f31/ft11"
};
const char * const riscv_excp_names[] = {
--
2.22.0
- [Qemu-devel] [PATCH v3 0/7] RISC-V: Hypervisor prep work part 2, Alistair Francis, 2019/08/15
- [Qemu-devel] [PATCH v3 1/7] target/riscv: Don't set write permissions on dirty PTEs, Alistair Francis, 2019/08/15
- [Qemu-devel] [PATCH v3 3/7] target/riscv: Create function to test if FP is enabled, Alistair Francis, 2019/08/15
- [Qemu-devel] [PATCH v3 2/7] riscv: plic: Remove unused interrupt functions, Alistair Francis, 2019/08/15
- [Qemu-devel] [PATCH v3 4/7] target/riscv: Update the Hypervisor CSRs to v0.4, Alistair Francis, 2019/08/15
- [Qemu-devel] [PATCH v3 5/7] target/riscv: Use both register name and ABI name,
Alistair Francis <=
- [Qemu-devel] [PATCH v3 6/7] target/riscv: Fix mstatus dirty mask, Alistair Francis, 2019/08/15
- [Qemu-devel] [PATCH v3 7/7] target/riscv: Convert mip to target_ulong, Alistair Francis, 2019/08/15
- Re: [Qemu-devel] [PATCH v3 0/7] RISC-V: Hypervisor prep work part 2, no-reply, 2019/08/15