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[Qemu-devel] [RFC PATCH v3 27/46] target/i386: introduce G*, R*, E* (gen
From: |
Jan Bobek |
Subject: |
[Qemu-devel] [RFC PATCH v3 27/46] target/i386: introduce G*, R*, E* (general register) operands |
Date: |
Wed, 14 Aug 2019 22:09:09 -0400 |
These address the general-purpose register file. The corresponding
32-bit or 64-bit register is passed as the operand value.
Signed-off-by: Jan Bobek <address@hidden>
---
target/i386/translate.c | 78 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 78 insertions(+)
diff --git a/target/i386/translate.c b/target/i386/translate.c
index 2374876b38..779b692942 100644
--- a/target/i386/translate.c
+++ b/target/i386/translate.c
@@ -4933,6 +4933,84 @@ DEF_INSNOP_ALIAS(Mq, M)
DEF_INSNOP_ALIAS(Mdq, M)
DEF_INSNOP_ALIAS(Mqq, M)
+/*
+ * 32-bit general register operands
+ */
+DEF_INSNOP_LDST(Gd, tcg_temp_i32, modrm_reg)
+DEF_INSNOP_LDST(Rd, tcg_temp_i32, modrm_rm_direct)
+
+INSNOP_LDST(tcg_temp_i32, modrm_reg)
+{
+ assert(0 <= ptr && ptr < CPU_NB_REGS);
+ if (is_write) {
+ tcg_gen_extu_i32_tl(cpu_regs[ptr], arg);
+ } else {
+ tcg_gen_trunc_tl_i32(arg, cpu_regs[ptr]);
+ }
+}
+INSNOP_LDST(tcg_temp_i32, modrm_rm_direct)
+{
+ insnop_ldst(tcg_temp_i32, modrm_reg)(env, s, modrm, is_write, arg, ptr);
+}
+
+DEF_INSNOP_LDST(MEd, tcg_temp_i32, Md)
+DEF_INSNOP_EITHER(Ed, Rd, MEd)
+DEF_INSNOP_LDST(MRdMw, tcg_temp_i32, Mw)
+DEF_INSNOP_EITHER(RdMw, Rd, MRdMw)
+
+INSNOP_LDST(tcg_temp_i32, Md)
+{
+ if (is_write) {
+ tcg_gen_qemu_st_i32(arg, ptr, s->mem_index, MO_LEUL);
+ } else {
+ tcg_gen_qemu_ld_i32(arg, ptr, s->mem_index, MO_LEUL);
+ }
+}
+INSNOP_LDST(tcg_temp_i32, Mw)
+{
+ if (is_write) {
+ tcg_gen_qemu_st_i32(arg, ptr, s->mem_index, MO_LEUW);
+ } else {
+ tcg_gen_qemu_ld_i32(arg, ptr, s->mem_index, MO_LEUW);
+ }
+}
+
+/*
+ * 64-bit general register operands
+ */
+DEF_INSNOP_LDST(Gq, tcg_temp_i64, modrm_reg)
+DEF_INSNOP_LDST(Rq, tcg_temp_i64, modrm_rm_direct)
+
+INSNOP_LDST(tcg_temp_i64, modrm_reg)
+{
+#ifdef TARGET_X86_64
+ assert(0 <= ptr && ptr < CPU_NB_REGS);
+ if (is_write) {
+ tcg_gen_mov_i64(cpu_regs[ptr], arg);
+ } else {
+ tcg_gen_mov_i64(arg, cpu_regs[ptr]);
+ }
+#else /* !TARGET_X86_64 */
+ g_assert_not_reached();
+#endif /* !TARGET_X86_64 */
+}
+INSNOP_LDST(tcg_temp_i64, modrm_rm_direct)
+{
+ insnop_ldst(tcg_temp_i64, modrm_reg)(env, s, modrm, is_write, arg, ptr);
+}
+
+DEF_INSNOP_LDST(MEq, tcg_temp_i64, Mq)
+DEF_INSNOP_EITHER(Eq, Rq, MEq)
+
+INSNOP_LDST(tcg_temp_i64, Mq)
+{
+ if (is_write) {
+ tcg_gen_qemu_st_i64(arg, ptr, s->mem_index, MO_LEQ);
+ } else {
+ tcg_gen_qemu_ld_i64(arg, ptr, s->mem_index, MO_LEQ);
+ }
+}
+
static void gen_sse_ng(CPUX86State *env, DisasContext *s, int b)
{
enum {
--
2.20.1
- [Qemu-devel] [RFC PATCH v3 16/46] target/i386: introduce instruction operand infrastructure, (continued)
- [Qemu-devel] [RFC PATCH v3 16/46] target/i386: introduce instruction operand infrastructure, Jan Bobek, 2019/08/14
- [Qemu-devel] [RFC PATCH v3 21/46] target/i386: introduce modrm operand, Jan Bobek, 2019/08/14
- [Qemu-devel] [RFC PATCH v3 18/46] target/i386: introduce generic either-or operand, Jan Bobek, 2019/08/14
- [Qemu-devel] [RFC PATCH v3 19/46] target/i386: introduce generic load-store operand, Jan Bobek, 2019/08/14
- [Qemu-devel] [RFC PATCH v3 20/46] target/i386: introduce tcg_temp operands, Jan Bobek, 2019/08/14
- [Qemu-devel] [RFC PATCH v3 22/46] target/i386: introduce operands for decoding modrm fields, Jan Bobek, 2019/08/14
- [Qemu-devel] [RFC PATCH v3 23/46] target/i386: introduce operand for direct-only r/m field, Jan Bobek, 2019/08/14
- [Qemu-devel] [RFC PATCH v3 25/46] target/i386: introduce Ib (immediate) operand, Jan Bobek, 2019/08/14
- [Qemu-devel] [RFC PATCH v3 29/46] target/i386: introduce H*, V*, U*, W* (SSE/AVX) operands, Jan Bobek, 2019/08/14
- [Qemu-devel] [RFC PATCH v3 28/46] target/i386: introduce P*, N*, Q* (MMX) operands, Jan Bobek, 2019/08/14
- [Qemu-devel] [RFC PATCH v3 27/46] target/i386: introduce G*, R*, E* (general register) operands,
Jan Bobek <=
- [Qemu-devel] [RFC PATCH v3 30/46] target/i386: introduce code generators, Jan Bobek, 2019/08/14
- [Qemu-devel] [RFC PATCH v3 33/46] target/i386: introduce sse-opcode.inc.h, Jan Bobek, 2019/08/14
- [Qemu-devel] [RFC PATCH v3 32/46] target/i386: introduce gvec-based code generator macros, Jan Bobek, 2019/08/14
- [Qemu-devel] [RFC PATCH v3 34/46] target/i386: introduce instruction translator macros, Jan Bobek, 2019/08/14
- [Qemu-devel] [RFC PATCH v3 24/46] target/i386: introduce operand vex_v, Jan Bobek, 2019/08/14
- [Qemu-devel] [RFC PATCH v3 26/46] target/i386: introduce M* (memptr) operands, Jan Bobek, 2019/08/14
- [Qemu-devel] [RFC PATCH v3 31/46] target/i386: introduce helper-based code generator macros, Jan Bobek, 2019/08/14
- [Qemu-devel] [RFC PATCH v3 35/46] target/i386: introduce MMX translators, Jan Bobek, 2019/08/14
- [Qemu-devel] [RFC PATCH v3 38/46] target/i386: introduce SSE translators, Jan Bobek, 2019/08/14
- [Qemu-devel] [RFC PATCH v3 37/46] target/i386: introduce MMX instructions to sse-opcode.inc.h, Jan Bobek, 2019/08/14