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Re: [Qemu-devel] [PATCH 08/28] riscv: sifive_u: Update PLIC hart topolog
From: |
Alistair Francis |
Subject: |
Re: [Qemu-devel] [PATCH 08/28] riscv: sifive_u: Update PLIC hart topology configuration string |
Date: |
Mon, 5 Aug 2019 17:17:08 -0700 |
On Mon, Aug 5, 2019 at 9:03 AM Bin Meng <address@hidden> wrote:
>
> With heterogeneous harts config, the PLIC hart topology configuration
> string are "M,MS,.." because of the monitor hart #0.
>
> Suggested-by: Fabien Chouteau <address@hidden>
> Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Alistair
> ---
>
> hw/riscv/sifive_u.c | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 206eccc..b235f29 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -372,10 +372,11 @@ static void riscv_sifive_u_soc_realize(DeviceState
> *dev, Error **errp)
> plic_hart_config = g_malloc0(plic_hart_config_len);
> for (i = 0; i < ms->smp.cpus; i++) {
> if (i != 0) {
> - strncat(plic_hart_config, ",", plic_hart_config_len);
> + strncat(plic_hart_config, "," SIFIVE_U_PLIC_HART_CONFIG,
> + plic_hart_config_len);
> + } else {
> + strncat(plic_hart_config, "M", plic_hart_config_len);
> }
> - strncat(plic_hart_config, SIFIVE_U_PLIC_HART_CONFIG,
> - plic_hart_config_len);
> plic_hart_config_len -= (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1);
> }
>
> --
> 2.7.4
>
>
- [Qemu-devel] [PATCH 04/28] riscv: hart: Extract hart realize to a separate routine, (continued)
- [Qemu-devel] [PATCH 04/28] riscv: hart: Extract hart realize to a separate routine, Bin Meng, 2019/08/05
- [Qemu-devel] [PATCH 05/28] riscv: hart: Support heterogeneous harts population, Bin Meng, 2019/08/05
- [Qemu-devel] [PATCH 07/28] riscv: sifive_u: Set the minimum number of cpus to 2, Bin Meng, 2019/08/05
- [Qemu-devel] [PATCH 09/28] riscv: sifive_u: Update UART base addresses, Bin Meng, 2019/08/05
- [Qemu-devel] [PATCH 06/28] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC, Bin Meng, 2019/08/05
- [Qemu-devel] [PATCH 08/28] riscv: sifive_u: Update PLIC hart topology configuration string, Bin Meng, 2019/08/05
- Re: [Qemu-devel] [PATCH 08/28] riscv: sifive_u: Update PLIC hart topology configuration string,
Alistair Francis <=
- [Qemu-devel] [PATCH 14/28] riscv: sifive: Implement PRCI model for FU540, Bin Meng, 2019/08/05
- [Qemu-devel] [PATCH 10/28] riscv: sifive_u: Remove the unnecessary include of prci header, Bin Meng, 2019/08/05
- [Qemu-devel] [PATCH 15/28] riscv: sifive_u: Generate hfclk and rtcclk nodes, Bin Meng, 2019/08/05
- [Qemu-devel] [PATCH 21/28] riscv: sifive_u: Update UART and ethernet node clock properties, Bin Meng, 2019/08/05
- [Qemu-devel] [PATCH 23/28] riscv: sifive: Move sifive_mmio_emulate() to a common place, Bin Meng, 2019/08/05
- [Qemu-devel] [PATCH 11/28] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}, Bin Meng, 2019/08/05
- [Qemu-devel] [PATCH 13/28] riscv: sifive_e: prci: Update the PRCI register block size, Bin Meng, 2019/08/05
- [Qemu-devel] [PATCH 18/28] riscv: hw: Implement a model for SiFive FU540 OTP, Bin Meng, 2019/08/05