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[Qemu-devel] [PATCH v3 09/34] target/arm: Add TTBR1_EL2
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v3 09/34] target/arm: Add TTBR1_EL2 |
Date: |
Sat, 3 Aug 2019 11:47:35 -0700 |
At the same time, add writefn to TTBR0_EL2 and TCR_EL2.
A later patch will update any ASID therein.
Reviewed-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/helper.c | 18 +++++++++++++-----
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 8baeb3f319..8d8b3cc40e 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -3449,6 +3449,12 @@ static void vmsa_ttbr_el1_write(CPUARMState *env, const
ARMCPRegInfo *ri,
}
}
+static void vmsa_tcr_ttbr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+ raw_write(env, ri, value);
+}
+
static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
@@ -4844,10 +4850,8 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
.resetvalue = 0 },
{ .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
- .access = PL2_RW,
- /* no .writefn needed as this can't cause an ASID change;
- * no .raw_writefn or .resetfn needed as we never use mask/base_mask
- */
+ .access = PL2_RW, .writefn = vmsa_tcr_ttbr_el2_write,
+ /* no .raw_writefn or .resetfn needed as we never use mask/base_mask */
.fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) },
{ .name = "VTCR", .state = ARM_CP_STATE_AA32,
.cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
@@ -4881,7 +4885,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
.fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[2]) },
{ .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
- .access = PL2_RW, .resetvalue = 0,
+ .access = PL2_RW, .resetvalue = 0, .writefn = vmsa_tcr_ttbr_el2_write,
.fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) },
{ .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
.access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
@@ -6807,6 +6811,10 @@ void register_cp_regs_for_features(ARMCPU *cpu)
.opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 1,
.access = PL2_RW,
.fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[2]) },
+ { .name = "TTBR1_EL2", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 1,
+ .access = PL2_RW, .writefn = vmsa_tcr_ttbr_el2_write,
+ .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el[2]) },
REGINFO_SENTINEL
};
define_arm_cp_regs(cpu, vhe_reginfo);
--
2.17.1
- [Qemu-devel] [PATCH v3 03/34] target/arm: Install ASIDs for long-form from EL1, (continued)
- [Qemu-devel] [PATCH v3 03/34] target/arm: Install ASIDs for long-form from EL1, Richard Henderson, 2019/08/03
- [Qemu-devel] [PATCH v3 04/34] target/arm: Install ASIDs for short-form from EL1, Richard Henderson, 2019/08/03
- [Qemu-devel] [PATCH v3 06/34] target/arm: Define isar_feature_aa64_vh, Richard Henderson, 2019/08/03
- [Qemu-devel] [PATCH v3 07/34] target/arm: Enable HCR_E2H for VHE, Richard Henderson, 2019/08/03
- [Qemu-devel] [PATCH v3 08/34] target/arm: Add CONTEXTIDR_EL2, Richard Henderson, 2019/08/03
- [Qemu-devel] [PATCH v3 11/34] target/arm: Add the hypervisor virtual counter, Richard Henderson, 2019/08/03
- [Qemu-devel] [PATCH v3 12/34] target/arm: Add VHE system register redirection and aliasing, Richard Henderson, 2019/08/03
- [Qemu-devel] [PATCH v3 14/34] target/arm: Simplify tlb_force_broadcast alternatives, Richard Henderson, 2019/08/03
- [Qemu-devel] [PATCH v3 10/34] target/arm: Update CNTVCT_EL0 for VHE, Richard Henderson, 2019/08/03
- [Qemu-devel] [PATCH v3 09/34] target/arm: Add TTBR1_EL2,
Richard Henderson <=
- [Qemu-devel] [PATCH v3 13/34] target/arm: Split out vae1_tlbmask, vmalle1_tlbmask, Richard Henderson, 2019/08/03
- [Qemu-devel] [PATCH v3 15/34] target/arm: Rename ARMMMUIdx*_S12NSE* to ARMMMUIdx*_E10_*, Richard Henderson, 2019/08/03
- [Qemu-devel] [PATCH v3 16/34] target/arm: Rename ARMMMUIdx_S2NS to ARMMMUIdx_Stage2, Richard Henderson, 2019/08/03
- [Qemu-devel] [PATCH v3 17/34] target/arm: Rename ARMMMUIdx_S1NSE* to ARMMMUIdx_Stage1_E*, Richard Henderson, 2019/08/03
- [Qemu-devel] [PATCH v3 19/34] target/arm: Rename ARMMMUIdx*_S1E3 to ARMMMUIdx*_SE3, Richard Henderson, 2019/08/03
- [Qemu-devel] [PATCH v3 18/34] target/arm: Rename ARMMMUIdx_S1SE* to ARMMMUIdx_SE*, Richard Henderson, 2019/08/03
- [Qemu-devel] [PATCH v3 23/34] target/arm: Update arm_mmu_idx for VHE, Richard Henderson, 2019/08/03
- [Qemu-devel] [PATCH v3 20/34] target/arm: Rename ARMMMUIdx_S1E2 to ARMMMUIdx_E2, Richard Henderson, 2019/08/03
- [Qemu-devel] [PATCH v3 22/34] target/arm: Add regime_has_2_ranges, Richard Henderson, 2019/08/03
- [Qemu-devel] [PATCH v3 21/34] target/arm: Reorganize ARMMMUIdx, Richard Henderson, 2019/08/03