Re: [Qemu-devel] [RISU RFC PATCH v2 06/14] x86.risu: add MMX instructions

[Richard Henderson]

On 7/10/19 8:29 PM, Jan Bobek wrote:
>>> +# Arithmetic Instructions
>>> +PADDB           MMX     00001111 11111100 !emit { modrm(); mem(size => 8); 
>>> }
>>> +PADDW           MMX     00001111 11111101 !emit { modrm(); mem(size => 8); 
>>> }
>>> +PADDD           MMX     00001111 11111110 !emit { modrm(); mem(size => 8); 
>>> }
>>> +PADDQ           MMX     00001111 11010100 !emit { modrm(); mem(size => 8); 
>>> }
> 
> Not this one, at least according to the Intel docs:
> 
> NP 0F D4 /r: PADDQ mm, mm/m64          (MMX)
> 66 0F D4 /r: PADDQ xmm1, xmm2/m128     (SSE2)
> 
> The SSE2 version is added in a later patch.

That's not how I read the Intel docs.

In the CPUID feature flag column of the MMX PADDQ, I see SSE2.  While the insn
affects the mmx registers, it was not added with the original MMX instruction 
set.


r~