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[Qemu-devel] [PATCH 10/11] target/hppa: exit TB if either Data or Instru
From: |
Sven Schnelle |
Subject: |
[Qemu-devel] [PATCH 10/11] target/hppa: exit TB if either Data or Instruction TLB changes |
Date: |
Mon, 11 Mar 2019 20:16:01 +0100 |
The current code assumes that we don't need to exit the TB
if a Data Cache Flush or Insert has happend. However, as we
have a shared Data/Instruction TLB, a Data cache flush also
flushes Instruction TLB entries, and a Data cache TLB insert
might also evict a Instruction TLB entry.
So exit the TB in all cases if Instruction translation is enabled.
Signed-off-by: Sven Schnelle <address@hidden>
---
target/hppa/translate.c | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index a393a12252..fcacff963e 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -2474,9 +2474,8 @@ static bool trans_ixtlbx(DisasContext *ctx, arg_ixtlbx *a)
gen_helper_itlbp(cpu_env, addr, reg);
}
- /* Exit TB for ITLB change if mmu is enabled. This *should* not be
- the case, since the OS TLB fill handler runs with mmu disabled. */
- if (!a->data && (ctx->tb_flags & PSW_C)) {
+ /* Exit TB for TLB change if mmu is enabled. */
+ if (ctx->tb_flags & PSW_C) {
ctx->base.is_jmp = DISAS_IAQ_N_STALE;
}
return nullify_end(ctx);
@@ -2503,7 +2502,7 @@ static bool trans_pxtlbx(DisasContext *ctx, arg_pxtlbx *a)
}
/* Exit TB for TLB change if mmu is enabled. */
- if (!a->data && (ctx->tb_flags & PSW_C)) {
+ if (ctx->tb_flags & PSW_C) {
ctx->base.is_jmp = DISAS_IAQ_N_STALE;
}
return nullify_end(ctx);
--
2.20.1
- [Qemu-devel] [PATCH 00/11] target/hppa patches, Sven Schnelle, 2019/03/11
- [Qemu-devel] [PATCH 11/11] target/hppa: call eval_interrupt() after ssm, Sven Schnelle, 2019/03/11
- [Qemu-devel] [PATCH 09/11] target/hppa: add TLB protection id check, Sven Schnelle, 2019/03/11
- [Qemu-devel] [PATCH 06/11] target/hppa: ignore DIAG opcode, Sven Schnelle, 2019/03/11
- [Qemu-devel] [PATCH 10/11] target/hppa: exit TB if either Data or Instruction TLB changes,
Sven Schnelle <=
- [Qemu-devel] [PATCH 07/11] target/hppa: fix b,gate instruction, Sven Schnelle, 2019/03/11
- [Qemu-devel] [PATCH 05/11] target/hppa: remove PSW I/R/Q bit check, Sven Schnelle, 2019/03/11
- [Qemu-devel] [PATCH 01/11] target/hppa: fix overwriting source reg in addb, Sven Schnelle, 2019/03/11
- [Qemu-devel] [PATCH 02/11] target/hppa: fix TLB handling for page 0, Sven Schnelle, 2019/03/11
- [Qemu-devel] [PATCH 03/11] target/hppa: report ITLB_EXCP_MISS for ITLB misses, Sven Schnelle, 2019/03/11