Re: [Qemu-devel] [RFC] multi phase reset

[Edgar E. Iglesias]

On Sun, Mar 03, 2019 at 10:59:30AM +0000, Peter Maydell wrote:
> On Sat, 2 Mar 2019 at 19:41, Philippe Mathieu-Daudé <address@hidden> wrote:
> >
> > Hi Damien,
> >
> > On 3/1/19 5:52 PM, Peter Maydell wrote:
> > > On Fri, 1 Mar 2019 at 15:34, Damien Hedde <address@hidden> wrote:
> > >> On 3/1/19 12:43 PM, Peter Maydell wrote:
> > >>> In my design the only thing that I thought would happen in phase 3
> > >>> was the "clear the resetting flag", but you've moved that to RELEASE.
> > >>> What's left ? Do you have a concrete example where we'd need this?
> > >>
> > >> I hesitated to remove this phase (would be easy to add it after if it is
> > >> really needed). I see 2 cases where it might be useful.
> >
> > If I RELEASE a PLL which need some time to warm up and stabilize, once
> > stabilized it moves the device to the POST phase where it is ready?
> 
> No, I think that things like that where the device is not ready
> for some period of time after reset should be handled by
> the device itself. Typically we just ignore this and have
> PLLs become stable instantaneously. If you really needed to
> model it you'd just have a timer of some kind inside the
> device model.

Right, this is how we tend to model things for the Xilinx parts. We usually 
don't care
about the delayed behaviour though.


> 
> (This matches h/w behaviour -- a PLL which is not yet stable
> is not still in reset, it's out of reset but has different
> behaviour for an initial period of time before it stabilizes.)
> 
> thanks
> -- PMM