Re: [Qemu-devel] [PATCH v7 20/35] target/riscv: Remove gen_jalr()

[Bastian Koppelmann]

On 2/13/19 4:53 PM, Palmer Dabbelt wrote:
> From: Bastian Koppelmann <address@hidden>
>
> trans_jalr() is the only caller, so move the code into trans_jalr().
>
> Acked-by: Alistair Francis <address@hidden>
> Reviewed-by: Richard Henderson <address@hidden>
> Signed-off-by: Bastian Koppelmann <address@hidden>
> Signed-off-by: Peer Adelt <address@hidden>
> ---
>   target/riscv/insn_trans/trans_rvi.inc.c | 28 +++++++++++++++++-
>   target/riscv/translate.c                | 38 -------------------------
>   2 files changed, 27 insertions(+), 39 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvi.inc.c 
> b/target/riscv/insn_trans/trans_rvi.inc.c
> index 4a23372cb823..39af38081ede 100644
> --- a/target/riscv/insn_trans/trans_rvi.inc.c
> +++ b/target/riscv/insn_trans/trans_rvi.inc.c
> @@ -42,7 +42,33 @@ static bool trans_jal(DisasContext *ctx, arg_jal *a)
>   
>   static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
>   {
> -    gen_jalr(ctx, OPC_RISC_JALR, a->rd, a->rs1, a->imm);
> +    /* no chaining with JALR */
> +    TCGLabel *misaligned = NULL;
> +    TCGv t0 = tcg_temp_new();
> +
> +
> +    gen_get_gpr(cpu_pc, a->rs1);
> +    tcg_gen_addi_tl(cpu_pc, cpu_pc, a->imm);
> +    tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2);
> +
> +    if (!riscv_has_ext(ctx->env, RVC)) {


Also has_ext()

Cheers,

Bastian