[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH v2 00/16] target-arm: Add GICv1/SecExt and GICv2/Gro
From: |
Greg Bellows |
Subject: |
[Qemu-devel] [PATCH v2 00/16] target-arm: Add GICv1/SecExt and GICv2/Grouping |
Date: |
Thu, 30 Oct 2014 17:11:56 -0500 |
This patch series adds ARM GICv1 and GICv2 security extension support. As a
result GIC interrupt grouping and FIQ enablement have also been added. FIQ
enablement is limited to ARM the ARM vexpress and virt machines.
At the current moment, the security extension capability is not enabled as it
depends on ARM secure address space support for proper operation. Instead,
secure checks are hardwired as non-secure.
v1 -> v2
- Fixed GIC_SET macro logic for group 0 and 1
- Fixed gic_update to use correct GIC_CTLR bit for group 1
- Reworked gic_set/get_cpu_control to better handle non-security extension case
for GICv1.
- Fixed various BPR read/write issues.
- Fixed EOIR ackctl issue.
- Fixed issue with gic_acknowledge not properly checking secure state.
- Fixed gic_update use of incorrect bit to check cpu_control group 1
enablement.
- Added clarifying comments
- Various fixes based on initial version review comments (see individual
patches for details).
Fabian Aggeler (15):
hw/intc/arm_gic: Request FIQ sources
hw/arm/vexpress.c: Wire FIQ between CPU <> GIC
hw/intc/arm_gic: Add Security Extensions property
hw/intc/arm_gic: Add ns_access() function
hw/intc/arm_gic: Add Interrupt Group Registers
hw/intc/arm_gic: Make ICDDCR/GICD_CTLR banked
hw/intc/arm_gic: Make ICCICR/GICC_CTLR banked
hw/intc/arm_gic: Make ICCBPR/GICC_BPR banked
hw/intc/arm_gic: Implement Non-secure view of RPR
hw/intc/arm_gic: Handle grouping for GICC_HPPIR
hw/intc/arm_gic: Change behavior of EOIR writes
hw/intc/arm_gic: Change behavior of IAR writes
hw/intc/arm_gic: Restrict priority view
hw/intc/arm_gic: Break out gic_update() function
hw/intc/arm_gic: add gic_update() for grouping
Greg Bellows (1):
hw/arm/virt.c: Wire FIQ between CPU <> GIC
hw/arm/vexpress.c | 2 +
hw/arm/virt.c | 2 +
hw/intc/arm_gic.c | 497 ++++++++++++++++++++++++++++++++++++---
hw/intc/arm_gic_common.c | 9 +-
hw/intc/arm_gic_kvm.c | 8 +-
hw/intc/armv7m_nvic.c | 2 +-
hw/intc/gic_internal.h | 25 ++
include/hw/intc/arm_gic_common.h | 23 +-
8 files changed, 526 insertions(+), 42 deletions(-)
--
1.8.3.2
- [Qemu-devel] [PATCH v2 00/16] target-arm: Add GICv1/SecExt and GICv2/Grouping,
Greg Bellows <=
- [Qemu-devel] [PATCH v2 15/16] hw/intc/arm_gic: Break out gic_update() function, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v2 14/16] hw/intc/arm_gic: Restrict priority view, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v2 11/16] hw/intc/arm_gic: Handle grouping for GICC_HPPIR, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v2 05/16] hw/intc/arm_gic: Add ns_access() function, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v2 01/16] hw/intc/arm_gic: Request FIQ sources, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v2 10/16] hw/intc/arm_gic: Implement Non-secure view of RPR, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v2 03/16] hw/arm/virt.c: Wire FIQ between CPU <> GIC, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v2 16/16] hw/intc/arm_gic: add gic_update() for grouping, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v2 08/16] hw/intc/arm_gic: Make ICCICR/GICC_CTLR banked, Greg Bellows, 2014/10/31
- [Qemu-devel] [PATCH v2 09/16] hw/intc/arm_gic: Make ICCBPR/GICC_BPR banked, Greg Bellows, 2014/10/31