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Re: [Qemu-devel] [PATCH v2 10/20] target-mips: add MSA I8 format instruc
From: |
James Hogan |
Subject: |
Re: [Qemu-devel] [PATCH v2 10/20] target-mips: add MSA I8 format instructions |
Date: |
Wed, 29 Oct 2014 11:38:19 +0000 |
User-agent: |
Mutt/1.5.22 (2013-10-16) |
On Wed, Oct 29, 2014 at 01:41:58AM +0000, Yongbok Kim wrote:
> add MSA I8 format instructions
>
> Reviewed-by: James Hogan <address@hidden>
The patch has changed quite a lot, so probably worth dropping
Reviewed-by in those cases in future.
> Signed-off-by: Yongbok Kim <address@hidden>
> +#define MSA_FN_IMM8(FUNC, DEST, OPERATION) \
> +void helper_msa_ ## FUNC(CPUMIPSState *env, uint32_t wd, uint32_t ws, \
> + uint32_t i8) \
> +{ \
> + wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \
> + wr_t *pws = &(env->active_fpu.fpr[ws].wr); \
> + uint32_t i; \
> + for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \
> + DEST = OPERATION; \
> + } \
I presume register partitioning isn't going to be supported in this
round of patches?
Okay.
> +}
> +
> +MSA_FN_IMM8(andi_b, pwd->b[i], pws->b[i] & i8)
> +MSA_FN_IMM8(ori_b, pwd->b[i], pws->b[i] | i8)
> +MSA_FN_IMM8(nori_b, pwd->b[i], ~(pws->b[i] | i8))
> +MSA_FN_IMM8(xori_b, pwd->b[i], pws->b[i] ^ i8)
> +
> +#define BIT_MOVE_IF_NOT_ZERO(dest, arg1, arg2, df) \
> + UNSIGNED(((dest & (~arg2)) | (arg1 & arg2)), df)
> +MSA_FN_IMM8(bmnzi_b, pwd->b[i], \
no need to escape the newline
> + BIT_MOVE_IF_NOT_ZERO(pwd->b[i], pws->b[i], i8, DF_BYTE))
> +
> +#define BIT_MOVE_IF_ZERO(dest, arg1, arg2, df) \
> + UNSIGNED((dest & arg2) | (arg1 & (~arg2)), df)
> +MSA_FN_IMM8(bmzi_b, pwd->b[i], \
same
> + BIT_MOVE_IF_ZERO(pwd->b[i], pws->b[i], i8, DF_BYTE))
> +
> +#define BIT_SELECT(dest, arg1, arg2, df) \
> + UNSIGNED((arg1 & (~dest)) | (arg2 & dest), df)
> +MSA_FN_IMM8(bseli_b, pwd->b[i], \
same
> + BIT_SELECT(pwd->b[i], pws->b[i], i8, DF_BYTE))
> +
> +#undef MSA_FN_IMM8
> +
> +#define SHF_POS(i, imm) ((i & 0xfc) + ((imm >> (2 * (i & 0x03))) & 0x03))
Should probably put brackets around macro arguments here, just for the
sake of robustness.
Otherwise
Reviewed-by: James Hogan <address@hidden>
Cheers
James
- Re: [Qemu-devel] [PATCH v2 04/20] target-mips: add 16, 64 bit load and store, (continued)
- [Qemu-devel] [PATCH v2 06/20] target-mips: add MSA opcode enum, Yongbok Kim, 2014/10/28
- [Qemu-devel] [PATCH v2 07/20] target-mips: add msa_reset(), global msa register, Yongbok Kim, 2014/10/28
- [Qemu-devel] [PATCH v2 08/20] target-mips: add msa_helper.c, Yongbok Kim, 2014/10/28
- [Qemu-devel] [PATCH v2 09/20] target-mips: add MSA branch instructions, Yongbok Kim, 2014/10/28
- [Qemu-devel] [PATCH v2 10/20] target-mips: add MSA I8 format instructions, Yongbok Kim, 2014/10/28
- Re: [Qemu-devel] [PATCH v2 10/20] target-mips: add MSA I8 format instructions,
James Hogan <=
- [Qemu-devel] [PATCH v2 11/20] target-mips: add MSA I5 format instruction, Yongbok Kim, 2014/10/28
- [Qemu-devel] [PATCH v2 12/20] target-mips: add MSA BIT format instructions, Yongbok Kim, 2014/10/28
- [Qemu-devel] [PATCH v2 14/20] target-mips: add MSA ELM format instructions, Yongbok Kim, 2014/10/28
- [Qemu-devel] [PATCH v2 13/20] target-mips: add MSA 3R format instructions, Yongbok Kim, 2014/10/28
- [Qemu-devel] [PATCH v2 16/20] target-mips: add MSA VEC/2R format instructions, Yongbok Kim, 2014/10/28
- [Qemu-devel] [PATCH v2 17/20] target-mips: add MSA 2RF format instructions, Yongbok Kim, 2014/10/28
- [Qemu-devel] [PATCH v2 18/20] target-mips: add MSA MI10 format instructions, Yongbok Kim, 2014/10/28