[Qemu-devel] [PATCH v2 11/15] target-tricore: Add instructions of SBC and SBRN opcode format

[Bastian Koppelmann]

Add instructions of SBC and SBRN opcode format.

Signed-off-by: Bastian Koppelmann <address@hidden>
---
v1 -> v2:
    - Change compare to 0 at instructions JZ_T and JNZ_T.
    - Group SBC instructions to one case.
    - Group SBRN instructions to one case.

 target-tricore/translate.c | 35 +++++++++++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)

diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index 403cf0c..bcc3392 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -247,6 +247,7 @@ static inline void gen_branch_condi(DisasContext *ctx, int 
cond, TCGv r1,
 static void gen_compute_branch(DisasContext *ctx, uint32_t opc,
                    int r1, int r2 , int32_t constant , int32_t offset)
 {
+    TCGv temp;

     switch (opc) {
 /* SB-format jumps */
@@ -263,6 +264,26 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t 
opc,
     case OPC1_16_SB_JNZ:
         gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], 0, offset);
         break;
+/* SBC-format jumps */
+    case OPC1_16_SBC_JEQ:
+        gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], constant, offset);
+        break;
+    case OPC1_16_SBC_JNE:
+        gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], constant, offset);
+        break;
+/* SBRN-format jumps */
+    case OPC1_16_SBRN_JZ_T:
+        temp = tcg_temp_new();
+        tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant);
+        gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset);
+        tcg_temp_free(temp);
+        break;
+    case OPC1_16_SBRN_JNZ_T:
+        temp = tcg_temp_new();
+        tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant);
+        gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset);
+        tcg_temp_free(temp);
+        break;
     default:
             printf("Branch Error at %x\n", ctx->pc);
     }
@@ -571,6 +592,20 @@ static void decode_16Bit_opc(CPUTRICOREState *env, 
DisasContext *ctx)
         address = MASK_OP_SB_DISP8_SEXT(ctx->opcode);
         gen_compute_branch(ctx, op1, 0, 0, 0, address);
         break;
+/* SBC-format */
+    case OPC1_16_SBC_JEQ:
+    case OPC1_16_SBC_JNE:
+        address = MASK_OP_SBC_DISP4(ctx->opcode);
+        const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode);
+        gen_compute_branch(ctx, op1, 0, 0, const16, address);
+        break;
+/* SBRN-format */
+    case OPC1_16_SBRN_JNZ_T:
+    case OPC1_16_SBRN_JZ_T:
+        address = MASK_OP_SBRN_DISP4(ctx->opcode);
+        const16 = MASK_OP_SBRN_N(ctx->opcode);
+        gen_compute_branch(ctx, op1, 0, 0, const16, address);
+        break;
     }
 }

--
2.0.1