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[Qemu-devel] [PATCH v2 7/8] target-arm: introduce be8 tbflag
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From: |
Paolo Bonzini |
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Subject: |
[Qemu-devel] [PATCH v2 7/8] target-arm: introduce be8 tbflag |
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Date: |
Thu, 29 May 2014 21:46:52 +0200 |
The tb flag for be8 mode comes from the CPSR E bit. This will let us
implement setend in the next patch.
Signed-off-by: Paolo Bonzini <address@hidden>
---
target-arm/cpu.h | 7 +++++++
target-arm/translate.c | 39 ++++++++++++++++++++++++---------------
target-arm/translate.h | 1 +
3 files changed, 32 insertions(+), 15 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 7d8332e..fbbb24e 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -1117,6 +1117,8 @@ static inline int cpu_mmu_index (CPUARMState *env)
#define ARM_TBFLAG_BSWAP_CODE_MASK (1 << ARM_TBFLAG_BSWAP_CODE_SHIFT)
#define ARM_TBFLAG_CPACR_FPEN_SHIFT 17
#define ARM_TBFLAG_CPACR_FPEN_MASK (1 << ARM_TBFLAG_CPACR_FPEN_SHIFT)
+#define ARM_TBFLAG_BE8_SHIFT 18
+#define ARM_TBFLAG_BE8_MASK (1 << ARM_TBFLAG_BE8_SHIFT)
/* Bit usage when in AArch64 state */
#define ARM_TBFLAG_AA64_EL_SHIFT 0
@@ -1143,6 +1145,8 @@ static inline int cpu_mmu_index (CPUARMState *env)
(((F) & ARM_TBFLAG_BSWAP_CODE_MASK) >> ARM_TBFLAG_BSWAP_CODE_SHIFT)
#define ARM_TBFLAG_CPACR_FPEN(F) \
(((F) & ARM_TBFLAG_CPACR_FPEN_MASK) >> ARM_TBFLAG_CPACR_FPEN_SHIFT)
+#define ARM_TBFLAG_BE8(F) \
+ (((F) & ARM_TBFLAG_BE8_MASK) >> ARM_TBFLAG_BE8_SHIFT)
#define ARM_TBFLAG_AA64_EL(F) \
(((F) & ARM_TBFLAG_AA64_EL_MASK) >> ARM_TBFLAG_AA64_EL_SHIFT)
#define ARM_TBFLAG_AA64_FPEN(F) \
@@ -1183,6 +1187,9 @@ static inline void cpu_get_tb_cpu_state(CPUARMState *env,
target_ulong *pc,
if (fpen == 3 || (fpen == 1 && arm_current_pl(env) != 0)) {
*flags |= ARM_TBFLAG_CPACR_FPEN_MASK;
}
+ if (env->uncached_cpsr & CPSR_E) {
+ *flags |= ARM_TBFLAG_BE8_MASK;
+ }
}
*cs_base = 0;
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 450be01..10030f3 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -840,23 +840,27 @@ static inline void store_reg_from_load(CPUARMState *env,
DisasContext *s,
#define DO_GEN_LD(SUFF, OPC) \
static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, TCGv_i32
addr, int index) \
{ \
- tcg_gen_qemu_ld_i32(val, addr, index, OPC); \
+ TCGMemOp opc = (OPC) | s->be8_op; \
+ tcg_gen_qemu_ld_i32(val, addr, index, opc); \
}
#define DO_GEN_ST(SUFF, OPC) \
static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val, TCGv_i32
addr, int index) \
{ \
- tcg_gen_qemu_st_i32(val, addr, index, OPC); \
+ TCGMemOp opc = (OPC) | s->be8_op; \
+ tcg_gen_qemu_st_i32(val, addr, index, opc); \
}
static inline void gen_aa32_ld64(DisasContext *s, TCGv_i64 val, TCGv_i32 addr,
int index)
{
- tcg_gen_qemu_ld_i64(val, addr, index, MO_TEQ);
+ TCGMemOp opc = MO_Q | s->be8_op;
+ tcg_gen_qemu_ld_i64(val, addr, index, opc);
}
static inline void gen_aa32_st64(DisasContext *s, TCGv_i64 val, TCGv_i32 addr,
int index)
{
- tcg_gen_qemu_st_i64(val, addr, index, MO_TEQ);
+ TCGMemOp opc = MO_Q | s->be8_op;
+ tcg_gen_qemu_st_i64(val, addr, index, opc);
}
#else
@@ -864,34 +868,38 @@ static inline void gen_aa32_st64(DisasContext *s,
TCGv_i64 val, TCGv_i32 addr, i
#define DO_GEN_LD(SUFF, OPC) \
static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, TCGv_i32
addr, int index) \
{ \
+ TCGMemOp opc = (OPC) | s->be8_op; \
TCGv addr64 = tcg_temp_new(); \
tcg_gen_extu_i32_i64(addr64, addr); \
- tcg_gen_qemu_ld_i32(val, addr64, index, OPC); \
+ tcg_gen_qemu_ld_i32(val, addr64, index, opc); \
tcg_temp_free(addr64); \
}
#define DO_GEN_ST(SUFF, OPC) \
static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val, TCGv_i32
addr, int index) \
{ \
+ TCGMemOp opc = (OPC) | s->be8_op; \
TCGv addr64 = tcg_temp_new(); \
tcg_gen_extu_i32_i64(addr64, addr); \
- tcg_gen_qemu_st_i32(val, addr64, index, OPC); \
+ tcg_gen_qemu_st_i32(val, addr64, index, opc); \
tcg_temp_free(addr64); \
}
static inline void gen_aa32_ld64(DisasContext *s, TCGv_i64 val, TCGv_i32 addr,
int index)
{
+ TCGMemOp opc = MO_Q | s->be8_op;
TCGv addr64 = tcg_temp_new();
tcg_gen_extu_i32_i64(addr64, addr);
- tcg_gen_qemu_ld_i64(val, addr64, index, MO_TEQ);
+ tcg_gen_qemu_ld_i64(val, addr64, index, opc);
tcg_temp_free(addr64);
}
static inline void gen_aa32_st64(DisasContext *s, TCGv_i64 val, TCGv_i32 addr,
int index)
{
+ TCGMemOp opc = MO_Q | s->be8_op;
TCGv addr64 = tcg_temp_new();
tcg_gen_extu_i32_i64(addr64, addr);
- tcg_gen_qemu_st_i64(val, addr64, index, MO_TEQ);
+ tcg_gen_qemu_st_i64(val, addr64, index, opc);
tcg_temp_free(addr64);
}
@@ -899,12 +907,12 @@ static inline void gen_aa32_st64(DisasContext *s,
TCGv_i64 val, TCGv_i32 addr, i
DO_GEN_LD(8s, MO_SB)
DO_GEN_LD(8u, MO_UB)
-DO_GEN_LD(16s, MO_TESW)
-DO_GEN_LD(16u, MO_TEUW)
-DO_GEN_LD(32u, MO_TEUL)
+DO_GEN_LD(16s, MO_SW)
+DO_GEN_LD(16u, MO_UW)
+DO_GEN_LD(32u, MO_UL)
DO_GEN_ST(8, MO_UB)
-DO_GEN_ST(16, MO_TEUW)
-DO_GEN_ST(32, MO_TEUL)
+DO_GEN_ST(16, MO_UW)
+DO_GEN_ST(32, MO_UL)
static inline void gen_set_pc_im(DisasContext *s, target_ulong val)
{
@@ -7446,7 +7454,7 @@ static void disas_arm_insn(CPUARMState * env,
DisasContext *s)
if ((insn & 0x0ffffdff) == 0x01010000) {
ARCH(6);
/* setend */
- if (((insn >> 9) & 1) != s->bswap_code) {
+ if (((insn >> 9) & 1) != (s->be8_op == MO_BE)) {
/* Dynamic endianness switching not implemented. */
qemu_log_mask(LOG_UNIMP, "arm: unimplemented setend\n");
goto illegal_op;
@@ -10603,7 +10611,7 @@ static void disas_thumb_insn(CPUARMState *env,
DisasContext *s)
case 2:
/* setend */
ARCH(6);
- if (((insn >> 3) & 1) != s->bswap_code) {
+ if (((insn >> 9) & 1) != (s->be8_op == MO_BE)) {
/* Dynamic endianness switching not implemented. */
qemu_log_mask(LOG_UNIMP, "arm: unimplemented setend\n");
goto illegal_op;
@@ -10784,6 +10792,7 @@ static inline void
gen_intermediate_code_internal(ARMCPU *cpu,
dc->aarch64 = 0;
dc->thumb = ARM_TBFLAG_THUMB(tb->flags);
dc->bswap_code = ARM_TBFLAG_BSWAP_CODE(tb->flags);
+ dc->be8_op = ARM_TBFLAG_BE8(tb->flags) ? MO_BE : MO_LE;
dc->condexec_mask = (ARM_TBFLAG_CONDEXEC(tb->flags) & 0xf) << 1;
dc->condexec_cond = ARM_TBFLAG_CONDEXEC(tb->flags) >> 4;
#if !defined(CONFIG_USER_ONLY)
diff --git a/target-arm/translate.h b/target-arm/translate.h
index 31a0104..ef23499 100644
--- a/target-arm/translate.h
+++ b/target-arm/translate.h
@@ -17,6 +17,7 @@ typedef struct DisasContext {
int singlestep_enabled;
int thumb;
int bswap_code;
+ TCGMemOp be8_op;
#if !defined(CONFIG_USER_ONLY)
int user;
#endif
--
1.9.3
- Re: [Qemu-devel] [PATCH v2 5/8] target-arm: implement SCTLR.EE, (continued)
- [Qemu-devel] [PATCH v2 2/8] linux-user: arm: set CPSR.E correctly for BE8 mode, Paolo Bonzini, 2014/05/29
- [Qemu-devel] [PATCH v2 4/8] linux-user: arm: handle CPSR.E correctly in strex emulation, Paolo Bonzini, 2014/05/29
- [Qemu-devel] [PATCH v2 3/8] linux-user: arm: pass env to get_user_code_*, Paolo Bonzini, 2014/05/29
- [Qemu-devel] [PATCH v2 6/8] target-arm: pass DisasContext to gen_aa32_ld*/st*, Paolo Bonzini, 2014/05/29
- [Qemu-devel] [PATCH v2 7/8] target-arm: introduce be8 tbflag,
Paolo Bonzini <=
- [Qemu-devel] [PATCH v2 8/8] target-arm: implement setend, Paolo Bonzini, 2014/05/29