[Qemu-devel] [PATCH target-arm v5 3/5] zynq_slcr: Implement CPU reset

[Peter Crosthwaite]

Implement the CPU reset IO line of the A9_CPU_RST_CTRL register
(offset 0x244). This is trivial GPIO mapping straight to the register
bits.

Signed-off-by: Peter Crosthwaite <address@hidden>
---
changed from v4:
Use GPIOs instead (PMM review)
changed from v3:
Author reset
Use CPU reset rather than device reset
use extract32 rather than << &.
Removed halting functionality
changed from v2:
used device halting API instead of talking to the cpu.

 hw/misc/zynq_slcr.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c
index e42a5b0..053b4b4 100644
--- a/hw/misc/zynq_slcr.c
+++ b/hw/misc/zynq_slcr.c
@@ -114,6 +114,10 @@ typedef enum {
   RESET_MAX
 } ResetValues;
 
+#define ZYNQ_SLCR_NUM_CPUS 2
+
+#define A9_CPU_RST_CTRL_RST_SHIFT 0
+
 #define TYPE_ZYNQ_SLCR "xilinx,zynq_slcr"
 #define ZYNQ_SLCR(obj) OBJECT_CHECK(ZynqSLCRState, (obj), TYPE_ZYNQ_SLCR)
 
@@ -121,6 +125,7 @@ typedef struct ZynqSLCRState {
     SysBusDevice parent_obj;
 
     MemoryRegion iomem;
+    qemu_irq cpu_resets[ZYNQ_SLCR_NUM_CPUS];
 
     union {
         struct {
@@ -345,6 +350,7 @@ static void zynq_slcr_write(void *opaque, hwaddr offset,
                           uint64_t val, unsigned size)
 {
     ZynqSLCRState *s = (ZynqSLCRState *)opaque;
+    int i;
 
     DB_PRINT("offset: %08x data: %08x\n", (unsigned)offset, (unsigned)val);
 
@@ -399,6 +405,14 @@ static void zynq_slcr_write(void *opaque, hwaddr offset,
                 goto bad_reg;
             }
             s->reset[(offset - 0x200) / 4] = val;
+            if (offset - 0x200 == A9_CPU * 4) { /* CPU Reset */
+                for (i = 0; i < ZYNQ_SLCR_NUM_CPUS; ++i) {
+                    bool rst = extract32(val, A9_CPU_RST_CTRL_RST_SHIFT + i, 
1);
+
+                    qemu_set_irq(s->cpu_resets[i], rst);
+                    DB_PRINT("%sresetting cpu %d\n", rst ? "un-" : "", i);
+                }
+            }
             break;
         case 0x300:
             s->apu_ctrl = val;
@@ -500,6 +514,8 @@ static int zynq_slcr_init(SysBusDevice *dev)
     memory_region_init_io(&s->iomem, OBJECT(s), &slcr_ops, s, "slcr", 0x1000);
     sysbus_init_mmio(dev, &s->iomem);
 
+    qdev_init_gpio_out(DEVICE(dev), s->cpu_resets, ZYNQ_SLCR_NUM_CPUS);
+
     return 0;
 }
 
-- 
1.8.5.3