[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH v1 04/11] char/cadence_uart: s/r_fifo/rx_fifo
From: |
Peter Crosthwaite |
Subject: |
[Qemu-devel] [PATCH v1 04/11] char/cadence_uart: s/r_fifo/rx_fifo |
Date: |
Mon, 16 Dec 2013 17:42:08 -0800 |
Rename this field to match the many other uses of "rx". Xilinx
docmentation (UG585) also refers to this as "RxFIFO".
Signed-off-by: Peter Crosthwaite <address@hidden>
---
hw/char/cadence_uart.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
index 263d31e..e12d50e 100644
--- a/hw/char/cadence_uart.c
+++ b/hw/char/cadence_uart.c
@@ -116,7 +116,7 @@ typedef struct {
MemoryRegion iomem;
uint32_t r[R_MAX];
- uint8_t r_fifo[RX_FIFO_SIZE];
+ uint8_t rx_fifo[RX_FIFO_SIZE];
uint32_t rx_wpos;
uint32_t rx_count;
uint64_t char_tx_time;
@@ -280,7 +280,7 @@ static void uart_write_rx_fifo(void *opaque, const uint8_t
*buf, int size)
s->r[R_CISR] |= UART_INTR_ROVR;
} else {
for (i = 0; i < size; i++) {
- s->r_fifo[s->rx_wpos] = buf[i];
+ s->rx_fifo[s->rx_wpos] = buf[i];
s->rx_wpos = (s->rx_wpos + 1) % RX_FIFO_SIZE;
s->rx_count++;
@@ -344,7 +344,7 @@ static void uart_read_rx_fifo(UartState *s, uint32_t *c)
if (s->rx_count) {
uint32_t rx_rpos =
(RX_FIFO_SIZE + s->rx_wpos - s->rx_count) % RX_FIFO_SIZE;
- *c = s->r_fifo[rx_rpos];
+ *c = s->rx_fifo[rx_rpos];
s->rx_count--;
if (!s->rx_count) {
@@ -492,7 +492,7 @@ static const VMStateDescription vmstate_cadence_uart = {
.post_load = cadence_uart_post_load,
.fields = (VMStateField[]) {
VMSTATE_UINT32_ARRAY(r, UartState, R_MAX),
- VMSTATE_UINT8_ARRAY(r_fifo, UartState, RX_FIFO_SIZE),
+ VMSTATE_UINT8_ARRAY(rx_fifo, UartState, RX_FIFO_SIZE),
VMSTATE_UINT32(rx_count, UartState),
VMSTATE_UINT32(rx_wpos, UartState),
VMSTATE_TIMER(fifo_trigger_handle, UartState),
--
1.8.5.1
- [Qemu-devel] [PATCH v1 00/11] Cadence UART cleanups and Tx path fixes, Peter Crosthwaite, 2013/12/16
- [Qemu-devel] [PATCH v1 01/11] char/cadence_uart: Mark struct fields as public/private, Peter Crosthwaite, 2013/12/16
- [Qemu-devel] [PATCH v1 02/11] char/cadence_uart: Add missing uart_update_state, Peter Crosthwaite, 2013/12/16
- [Qemu-devel] [PATCH v1 03/11] char/cadence_uart: Fix reset., Peter Crosthwaite, 2013/12/16
- [Qemu-devel] [PATCH v1 04/11] char/cadence_uart: s/r_fifo/rx_fifo,
Peter Crosthwaite <=
- [Qemu-devel] [PATCH v1 05/11] char/cadence_uart: Simplify status generation, Peter Crosthwaite, 2013/12/16
- [Qemu-devel] [PATCH v1 06/11] char/cadence_uart: Define Missing SR/ISR fields, Peter Crosthwaite, 2013/12/16
- [Qemu-devel] [PATCH v1 07/11] char/cadence_uart: Remove TX timer & add TX FIFO state, Peter Crosthwaite, 2013/12/16
- [Qemu-devel] [PATCH v1 08/11] char/cadence_uart: Fix can_receive logic, Peter Crosthwaite, 2013/12/16
- [Qemu-devel] [PATCH v1 09/11] char/cadence_uart: Use the TX fifo for transmission, Peter Crosthwaite, 2013/12/16
- [Qemu-devel] [PATCH v1 10/11] char/cadence_uart: Delete redundant rx rst logic, Peter Crosthwaite, 2013/12/16
- [Qemu-devel] [PATCH v1 11/11] char/cadence_uart: Implement Tx flow control, Peter Crosthwaite, 2013/12/16