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[Qemu-devel] [PATCH 09/18] softfloat: Fix Handling of Small Negatives in
From: |
Tom Musta |
Subject: |
[Qemu-devel] [PATCH 09/18] softfloat: Fix Handling of Small Negatives in float64_to_uint64 |
Date: |
Mon, 9 Dec 2013 09:47:06 -0600 |
The float64_to_uint64 routine exits early for all negative numbers.
While the integer result is always correctly returned as 0, the
exception flags are also always set to float_flag_invalid. This
is incorrect for those cases where a small negative number (-1 < x < 0)
rounds to zero. In such a case, the flag should be reported as
inexact.
The following patch allows these small numbers to flow through the
rounding and packing code.
Some interesting test patterns are:
(1) BC6AEEBA7F390215 / -0x1.aeeba7f390215p-57, round to nearest
even should round up to zero (inexact)
(2) A66A44F252C9AAAC /-0x1.a44f252c9aaacp-409 round up should round
up to zero (inexact)
(3) B4692F3AFFAF2716 / -0x1.92f3affaf2716p-185 round down should
be invalid.
Signed-off-by: Tom Musta <address@hidden>
---
fpu/softfloat.c | 41 +++++++++++++++++++++--------------------
1 files changed, 21 insertions(+), 20 deletions(-)
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index cb03dca..3d7a8ff 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -161,7 +161,6 @@ static int32 roundAndPackInt32( flag zSign, uint64_t absZ
STATUS_PARAM)
| exception is raised and the largest positive or negative integer is
| returned.
*----------------------------------------------------------------------------*/
-
static int64 roundAndPackInt64( flag zSign, uint64_t absZ0, uint64_t absZ1
STATUS_PARAM)
{
int8 roundingMode;
@@ -213,20 +212,24 @@ static int64 roundAndPackInt64( flag zSign, uint64_t
absZ0, uint64_t absZ1 STATU
| exception is raised and the largest unsigned integer is returned.
*----------------------------------------------------------------------------*/
-static int64 roundAndPackUint64(uint64_t absZ0, uint64_t absZ1 STATUS_PARAM)
+static int64 roundAndPackUint64(flag zSign, uint64_t absZ0,
+ uint64_t absZ1 STATUS_PARAM)
{
int8 roundingMode;
flag roundNearestEven, increment;
- int64_t z;
roundingMode = STATUS(float_rounding_mode);
roundNearestEven = (roundingMode == float_round_nearest_even);
- increment = ((int64_t) absZ1 < 0);
+ increment = ((int64_t)absZ1 < 0);
if (!roundNearestEven) {
if (roundingMode == float_round_to_zero) {
increment = 0;
- } else {
- increment = (roundingMode == float_round_up) && absZ1;
+ } else if (absZ1) {
+ if (zSign) {
+ increment = (roundingMode == float_round_down) && absZ1;
+ } else {
+ increment = (roundingMode == float_round_up) && absZ1;
+ }
}
}
if (increment) {
@@ -237,11 +240,16 @@ static int64 roundAndPackUint64(uint64_t absZ0, uint64_t
absZ1 STATUS_PARAM)
}
absZ0 &= ~(((uint64_t)(absZ1<<1) == 0) & roundNearestEven);
}
- z = absZ0;
+
+ if (zSign && absZ0) {
+ float_raise(float_flag_invalid STATUS_VAR);
+ return 0;
+ }
+
if (absZ1) {
STATUS(float_exception_flags) |= float_flag_inexact;
}
- return z;
+ return absZ0;
}
/*----------------------------------------------------------------------------
@@ -1590,7 +1598,7 @@ uint64 float32_to_uint64(float32 a STATUS_PARAM)
aSig64 = aSig;
aSig64 <<= 40;
shift64ExtraRightJamming(aSig64, 0, shiftCount, &aSig64, &aSigExtra);
- return roundAndPackUint64(aSig64, aSigExtra STATUS_VAR);
+ return roundAndPackUint64(aSign, aSig64, aSigExtra STATUS_VAR);
}
/*----------------------------------------------------------------------------
@@ -6643,12 +6651,8 @@ uint64_t float64_to_uint64(float64 a STATUS_PARAM)
aSig = extractFloat64Frac(a);
aExp = extractFloat64Exp(a);
aSign = extractFloat64Sign(a);
- if (aSign) {
- if (aExp) {
- float_raise(float_flag_invalid STATUS_VAR);
- } else if (aSig) { /* negative denormalized */
- float_raise(float_flag_inexact STATUS_VAR);
- }
+ if (aSign && (aExp > 1022)) {
+ float_raise(float_flag_invalid STATUS_VAR);
return 0;
}
if (aExp) {
@@ -6657,10 +6661,7 @@ uint64_t float64_to_uint64(float64 a STATUS_PARAM)
shiftCount = 0x433 - aExp;
if (shiftCount <= 0) {
if (0x43E < aExp) {
- if ((aSig != LIT64(0x0010000000000000)) ||
- (aExp == 0x7FF)) {
- float_raise(float_flag_invalid STATUS_VAR);
- }
+ float_raise(float_flag_invalid STATUS_VAR);
return LIT64(0xFFFFFFFFFFFFFFFF);
}
aSigExtra = 0;
@@ -6668,7 +6669,7 @@ uint64_t float64_to_uint64(float64 a STATUS_PARAM)
} else {
shift64ExtraRightJamming(aSig, 0, shiftCount, &aSig, &aSigExtra);
}
- return roundAndPackUint64(aSig, aSigExtra STATUS_VAR);
+ return roundAndPackUint64(aSign, aSig, aSigExtra STATUS_VAR);
}
--
1.7.1
[Qemu-devel] [PATCH 10/18] softfloat: Fix float64_to_uint64_round_to_zero, Tom Musta, 2013/12/09
[Qemu-devel] [PATCH 11/18] softfloat: Fix float64_to_uint32, Tom Musta, 2013/12/09
[Qemu-devel] [PATCH 12/18] softfloat: Fix float64_to_uint32_round_to_zero, Tom Musta, 2013/12/09
[Qemu-devel] [PATCH 13/18] target-ppc: Add ISA 2.06 fcfid[u][s] Instructions, Tom Musta, 2013/12/09
[Qemu-devel] [PATCH 14/18] target-ppc: Fix and enable fri[mnpz], Tom Musta, 2013/12/09
[Qemu-devel] [PATCH 15/18] target-ppc: Add ISA 2.06 ftdiv Instruction, Tom Musta, 2013/12/09