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[Qemu-devel] [PATCH v3 11/13] host-utils: add clrsb32/64 - count leading
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH v3 11/13] host-utils: add clrsb32/64 - count leading redundant sign bits |
Date: |
Mon, 9 Dec 2013 12:37:32 +0000 |
From: Claudio Fontana <address@hidden>
this patch introduces wrappers for the clrsb builtins,
which count the leading redundant sign bits.
Signed-off-by: Claudio Fontana <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
include/qemu/host-utils.h | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/include/qemu/host-utils.h b/include/qemu/host-utils.h
index 0f688c1..de85d28 100644
--- a/include/qemu/host-utils.h
+++ b/include/qemu/host-utils.h
@@ -228,6 +228,38 @@ static inline int cto64(uint64_t val)
}
/**
+ * clrsb32 - count leading redundant sign bits in a 32-bit value.
+ * @val: The value to search
+ *
+ * Returns the number of bits following the sign bit that are equal to it.
+ * No special cases; output range is [0-31].
+ */
+static inline int clrsb32(uint32_t val)
+{
+#if QEMU_GNUC_PREREQ(4, 7)
+ return __builtin_clrsb(val);
+#else
+ return clz32(val ^ ((int32_t)val >> 1)) - 1;
+#endif
+}
+
+/**
+ * clrsb64 - count leading redundant sign bits in a 64-bit value.
+ * @val: The value to search
+ *
+ * Returns the number of bits following the sign bit that are equal to it.
+ * No special cases; output range is [0-63].
+ */
+static inline int clrsb64(uint64_t val)
+{
+#if QEMU_GNUC_PREREQ(4, 7)
+ return __builtin_clrsbll(val);
+#else
+ return clz64(val ^ ((int64_t)val >> 1)) - 1;
+#endif
+}
+
+/**
* ctpop8 - count the population of one bits in an 8-bit value.
* @val: The value to search
*/
--
1.8.5
- [Qemu-devel] [PATCH v3 00/13] target-arm: A64 decoder set 2: misc logic and bit ops, Peter Maydell, 2013/12/09
- [Qemu-devel] [PATCH v3 04/13] target-arm: A64: add support for EXTR, Peter Maydell, 2013/12/09
- [Qemu-devel] [PATCH v3 10/13] target-arm: A64: add support for bitfield insns, Peter Maydell, 2013/12/09
- [Qemu-devel] [PATCH v3 11/13] host-utils: add clrsb32/64 - count leading redundant sign bits,
Peter Maydell <=
- [Qemu-devel] [PATCH v3 01/13] target-arm: A64: add support for conditional select, Peter Maydell, 2013/12/09
- [Qemu-devel] [PATCH v3 08/13] target-arm: A64: add support for 1-src RBIT insn, Peter Maydell, 2013/12/09
- [Qemu-devel] [PATCH v3 05/13] target-arm: A64: add support for 2-src data processing and DIV, Peter Maydell, 2013/12/09
- [Qemu-devel] [PATCH v3 12/13] target-arm: A64: add support for 1-src CLS insn, Peter Maydell, 2013/12/09
- [Qemu-devel] [PATCH v3 07/13] target-arm: A64: add support for 1-src data processing and CLZ, Peter Maydell, 2013/12/09
- [Qemu-devel] [PATCH v3 06/13] target-arm: A64: add support for 2-src shift reg insns, Peter Maydell, 2013/12/09
- [Qemu-devel] [PATCH v3 02/13] target-arm: A64: add support for logical (shifted register), Peter Maydell, 2013/12/09
- [Qemu-devel] [PATCH v3 13/13] target-arm: A64: add support for logical (immediate) insns, Peter Maydell, 2013/12/09
- [Qemu-devel] [PATCH v3 09/13] target-arm: A64: add support for 1-src REV insns, Peter Maydell, 2013/12/09