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[Qemu-devel] [RFC PATCH 14/21] target-arm: split TLB for secure state
|
From: |
Sergey Fedorov |
|
Subject: |
[Qemu-devel] [RFC PATCH 14/21] target-arm: split TLB for secure state |
|
Date: |
Tue, 03 Dec 2013 12:48:48 +0400 |
This patch is based on idea found in patch at
git://github.com/jowinter/qemu-trustzone.git
a9ad01767c4b25e14700b5682a412f4fd8146ee8 by
Johannes Winter <address@hidden>.
Each secure state has its own MMU state. So provide a separate TLB for
each secure state to avoid flushing the whole TLB on each secure state
change. Do not use IS_USER() macro anymore as MMU index in translation
code. Use new MEM_INDEX() and MEM_INDEX_USER() macros instead.
Signed-off-by: Sergey Fedorov <address@hidden>
---
target-arm/cpu.h | 14 ++-
target-arm/helper.c | 2 +-
target-arm/translate.c | 247 +++++++++++++++++++++++++-----------------------
target-arm/translate.h | 1 +
4 files changed, 140 insertions(+), 124 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index ffc1b21..a20f354 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -75,7 +75,7 @@ typedef uint32_t ARMReadCPFunc(void *opaque, int cp_info,
struct arm_boot_info;
-#define NB_MMU_MODES 2
+#define NB_MMU_MODES 4
/* We currently assume float and double are IEEE single and double
precision respectively.
@@ -827,10 +827,18 @@ static inline CPUARMState *cpu_init(const char *cpu_model)
/* MMU modes definitions */
#define MMU_MODE0_SUFFIX _kernel
#define MMU_MODE1_SUFFIX _user
-#define MMU_USER_IDX 1
+#define MMU_MODE2_SUFFIX _ns_kernel
+#define MMU_MODE3_SUFFIX _ns_user
+#define MMU_USER_BIT 1
+#define MMU_NS_BIT 2
+#define MMU_KERN_IDX (0)
+#define MMU_USER_IDX (MMU_USER_BIT)
+#define MMU_NS_KERN_IDX (MMU_NS_BIT | MMU_KERN_IDX)
+#define MMU_NS_USER_IDX (MMU_NS_BIT | MMU_USER_IDX)
static inline int cpu_mmu_index (CPUARMState *env)
{
- return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0;
+ return (arm_is_secure(env) << 1) |
+ ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR);
}
#include "exec/cpu-all.h"
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 780d0a0..c145cfe 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -3141,7 +3141,7 @@ int cpu_arm_handle_mmu_fault (CPUARMState *env,
target_ulong address,
int prot;
int ret, is_user;
- is_user = mmu_idx == MMU_USER_IDX;
+ is_user = mmu_idx & MMU_USER_BIT;
ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot,
&page_size);
if (ret == 0) {
diff --git a/target-arm/translate.c b/target-arm/translate.c
index b3615fc..8548a4c 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -53,9 +53,13 @@ static uint32_t gen_opc_condexec_bits[OPC_BUF_SIZE];
#if defined(CONFIG_USER_ONLY)
#define IS_USER(s) 1
#define IS_NS(s) 1
+#define MEM_INDEX(s) MMU_USER_IDX
+#define MEM_INDEX_USER(S) MMU_USER_IDX
#else
#define IS_USER(s) (s->user)
#define IS_NS(s) (s->ns)
+#define MEM_INDEX(s) (s->mem_idx)
+#define MEM_INDEX_USER(S) (MEM_INDEX(s) | MMU_USER_BIT)
#endif
/* These instructions trap after executing, so defer them until after the
@@ -1140,18 +1144,18 @@ VFP_GEN_FIX(ulto)
static inline void gen_vfp_ld(DisasContext *s, int dp, TCGv_i32 addr)
{
if (dp) {
- gen_aa32_ld64(cpu_F0d, addr, IS_USER(s));
+ gen_aa32_ld64(cpu_F0d, addr, MEM_INDEX(s));
} else {
- gen_aa32_ld32u(cpu_F0s, addr, IS_USER(s));
+ gen_aa32_ld32u(cpu_F0s, addr, MEM_INDEX(s));
}
}
static inline void gen_vfp_st(DisasContext *s, int dp, TCGv_i32 addr)
{
if (dp) {
- gen_aa32_st64(cpu_F0d, addr, IS_USER(s));
+ gen_aa32_st64(cpu_F0d, addr, MEM_INDEX(s));
} else {
- gen_aa32_st32(cpu_F0s, addr, IS_USER(s));
+ gen_aa32_st32(cpu_F0s, addr, MEM_INDEX(s));
}
}
@@ -1489,24 +1493,24 @@ static int disas_iwmmxt_insn(CPUARMState *env,
DisasContext *s, uint32_t insn)
if (insn & ARM_CP_RW_BIT) {
if ((insn >> 28) == 0xf) { /* WLDRW wCx */
tmp = tcg_temp_new_i32();
- gen_aa32_ld32u(tmp, addr, IS_USER(s));
+ gen_aa32_ld32u(tmp, addr, MEM_INDEX(s));
iwmmxt_store_creg(wrd, tmp);
} else {
i = 1;
if (insn & (1 << 8)) {
if (insn & (1 << 22)) { /* WLDRD */
- gen_aa32_ld64(cpu_M0, addr, IS_USER(s));
+ gen_aa32_ld64(cpu_M0, addr, MEM_INDEX(s));
i = 0;
} else { /* WLDRW wRd */
tmp = tcg_temp_new_i32();
- gen_aa32_ld32u(tmp, addr, IS_USER(s));
+ gen_aa32_ld32u(tmp, addr, MEM_INDEX(s));
}
} else {
tmp = tcg_temp_new_i32();
if (insn & (1 << 22)) { /* WLDRH */
- gen_aa32_ld16u(tmp, addr, IS_USER(s));
+ gen_aa32_ld16u(tmp, addr, MEM_INDEX(s));
} else { /* WLDRB */
- gen_aa32_ld8u(tmp, addr, IS_USER(s));
+ gen_aa32_ld8u(tmp, addr, MEM_INDEX(s));
}
}
if (i) {
@@ -1518,24 +1522,24 @@ static int disas_iwmmxt_insn(CPUARMState *env,
DisasContext *s, uint32_t insn)
} else {
if ((insn >> 28) == 0xf) { /* WSTRW wCx */
tmp = iwmmxt_load_creg(wrd);
- gen_aa32_st32(tmp, addr, IS_USER(s));
+ gen_aa32_st32(tmp, addr, MEM_INDEX(s));
} else {
gen_op_iwmmxt_movq_M0_wRn(wrd);
tmp = tcg_temp_new_i32();
if (insn & (1 << 8)) {
if (insn & (1 << 22)) { /* WSTRD */
- gen_aa32_st64(cpu_M0, addr, IS_USER(s));
+ gen_aa32_st64(cpu_M0, addr, MEM_INDEX(s));
} else { /* WSTRW wRd */
tcg_gen_trunc_i64_i32(tmp, cpu_M0);
- gen_aa32_st32(tmp, addr, IS_USER(s));
+ gen_aa32_st32(tmp, addr, MEM_INDEX(s));
}
} else {
if (insn & (1 << 22)) { /* WSTRH */
tcg_gen_trunc_i64_i32(tmp, cpu_M0);
- gen_aa32_st16(tmp, addr, IS_USER(s));
+ gen_aa32_st16(tmp, addr, MEM_INDEX(s));
} else { /* WSTRB */
tcg_gen_trunc_i64_i32(tmp, cpu_M0);
- gen_aa32_st8(tmp, addr, IS_USER(s));
+ gen_aa32_st8(tmp, addr, MEM_INDEX(s));
}
}
}
@@ -2600,15 +2604,15 @@ static TCGv_i32 gen_load_and_replicate(DisasContext *s,
TCGv_i32 addr, int size)
TCGv_i32 tmp = tcg_temp_new_i32();
switch (size) {
case 0:
- gen_aa32_ld8u(tmp, addr, IS_USER(s));
+ gen_aa32_ld8u(tmp, addr, MEM_INDEX(s));
gen_neon_dup_u8(tmp, 0);
break;
case 1:
- gen_aa32_ld16u(tmp, addr, IS_USER(s));
+ gen_aa32_ld16u(tmp, addr, MEM_INDEX(s));
gen_neon_dup_low16(tmp);
break;
case 2:
- gen_aa32_ld32u(tmp, addr, IS_USER(s));
+ gen_aa32_ld32u(tmp, addr, MEM_INDEX(s));
break;
default: /* Avoid compiler warnings. */
abort();
@@ -3886,11 +3890,11 @@ static int disas_neon_ls_insn(CPUARMState * env,
DisasContext *s, uint32_t insn)
if (size == 3) {
tmp64 = tcg_temp_new_i64();
if (load) {
- gen_aa32_ld64(tmp64, addr, IS_USER(s));
+ gen_aa32_ld64(tmp64, addr, MEM_INDEX(s));
neon_store_reg64(tmp64, rd);
} else {
neon_load_reg64(tmp64, rd);
- gen_aa32_st64(tmp64, addr, IS_USER(s));
+ gen_aa32_st64(tmp64, addr, MEM_INDEX(s));
}
tcg_temp_free_i64(tmp64);
tcg_gen_addi_i32(addr, addr, stride);
@@ -3899,21 +3903,21 @@ static int disas_neon_ls_insn(CPUARMState * env,
DisasContext *s, uint32_t insn)
if (size == 2) {
if (load) {
tmp = tcg_temp_new_i32();
- gen_aa32_ld32u(tmp, addr, IS_USER(s));
+ gen_aa32_ld32u(tmp, addr, MEM_INDEX(s));
neon_store_reg(rd, pass, tmp);
} else {
tmp = neon_load_reg(rd, pass);
- gen_aa32_st32(tmp, addr, IS_USER(s));
+ gen_aa32_st32(tmp, addr, MEM_INDEX(s));
tcg_temp_free_i32(tmp);
}
tcg_gen_addi_i32(addr, addr, stride);
} else if (size == 1) {
if (load) {
tmp = tcg_temp_new_i32();
- gen_aa32_ld16u(tmp, addr, IS_USER(s));
+ gen_aa32_ld16u(tmp, addr, MEM_INDEX(s));
tcg_gen_addi_i32(addr, addr, stride);
tmp2 = tcg_temp_new_i32();
- gen_aa32_ld16u(tmp2, addr, IS_USER(s));
+ gen_aa32_ld16u(tmp2, addr, MEM_INDEX(s));
tcg_gen_addi_i32(addr, addr, stride);
tcg_gen_shli_i32(tmp2, tmp2, 16);
tcg_gen_or_i32(tmp, tmp, tmp2);
@@ -3923,10 +3927,10 @@ static int disas_neon_ls_insn(CPUARMState * env,
DisasContext *s, uint32_t insn)
tmp = neon_load_reg(rd, pass);
tmp2 = tcg_temp_new_i32();
tcg_gen_shri_i32(tmp2, tmp, 16);
- gen_aa32_st16(tmp, addr, IS_USER(s));
+ gen_aa32_st16(tmp, addr, MEM_INDEX(s));
tcg_temp_free_i32(tmp);
tcg_gen_addi_i32(addr, addr, stride);
- gen_aa32_st16(tmp2, addr, IS_USER(s));
+ gen_aa32_st16(tmp2, addr, MEM_INDEX(s));
tcg_temp_free_i32(tmp2);
tcg_gen_addi_i32(addr, addr, stride);
}
@@ -3935,7 +3939,7 @@ static int disas_neon_ls_insn(CPUARMState * env,
DisasContext *s, uint32_t insn)
TCGV_UNUSED_I32(tmp2);
for (n = 0; n < 4; n++) {
tmp = tcg_temp_new_i32();
- gen_aa32_ld8u(tmp, addr, IS_USER(s));
+ gen_aa32_ld8u(tmp, addr, MEM_INDEX(s));
tcg_gen_addi_i32(addr, addr, stride);
if (n == 0) {
tmp2 = tmp;
@@ -3955,7 +3959,7 @@ static int disas_neon_ls_insn(CPUARMState * env,
DisasContext *s, uint32_t insn)
} else {
tcg_gen_shri_i32(tmp, tmp2, n * 8);
}
- gen_aa32_st8(tmp, addr, IS_USER(s));
+ gen_aa32_st8(tmp, addr, MEM_INDEX(s));
tcg_temp_free_i32(tmp);
tcg_gen_addi_i32(addr, addr, stride);
}
@@ -4079,13 +4083,13 @@ static int disas_neon_ls_insn(CPUARMState * env,
DisasContext *s, uint32_t insn)
tmp = tcg_temp_new_i32();
switch (size) {
case 0:
- gen_aa32_ld8u(tmp, addr, IS_USER(s));
+ gen_aa32_ld8u(tmp, addr, MEM_INDEX(s));
break;
case 1:
- gen_aa32_ld16u(tmp, addr, IS_USER(s));
+ gen_aa32_ld16u(tmp, addr, MEM_INDEX(s));
break;
case 2:
- gen_aa32_ld32u(tmp, addr, IS_USER(s));
+ gen_aa32_ld32u(tmp, addr, MEM_INDEX(s));
break;
default: /* Avoid compiler warnings. */
abort();
@@ -4103,13 +4107,13 @@ static int disas_neon_ls_insn(CPUARMState * env,
DisasContext *s, uint32_t insn)
tcg_gen_shri_i32(tmp, tmp, shift);
switch (size) {
case 0:
- gen_aa32_st8(tmp, addr, IS_USER(s));
+ gen_aa32_st8(tmp, addr, MEM_INDEX(s));
break;
case 1:
- gen_aa32_st16(tmp, addr, IS_USER(s));
+ gen_aa32_st16(tmp, addr, MEM_INDEX(s));
break;
case 2:
- gen_aa32_st32(tmp, addr, IS_USER(s));
+ gen_aa32_st32(tmp, addr, MEM_INDEX(s));
break;
}
tcg_temp_free_i32(tmp);
@@ -6550,14 +6554,14 @@ static void gen_load_exclusive(DisasContext *s, int rt,
int rt2,
switch (size) {
case 0:
- gen_aa32_ld8u(tmp, addr, IS_USER(s));
+ gen_aa32_ld8u(tmp, addr, MEM_INDEX(s));
break;
case 1:
- gen_aa32_ld16u(tmp, addr, IS_USER(s));
+ gen_aa32_ld16u(tmp, addr, MEM_INDEX(s));
break;
case 2:
case 3:
- gen_aa32_ld32u(tmp, addr, IS_USER(s));
+ gen_aa32_ld32u(tmp, addr, MEM_INDEX(s));
break;
default:
abort();
@@ -6568,7 +6572,7 @@ static void gen_load_exclusive(DisasContext *s, int rt,
int rt2,
TCGv_i32 tmp2 = tcg_temp_new_i32();
tcg_gen_addi_i32(tmp2, addr, 4);
tmp = tcg_temp_new_i32();
- gen_aa32_ld32u(tmp, tmp2, IS_USER(s));
+ gen_aa32_ld32u(tmp, tmp2, MEM_INDEX(s));
tcg_temp_free_i32(tmp2);
tcg_gen_mov_i32(cpu_exclusive_high, tmp);
store_reg(s, rt2, tmp);
@@ -6610,14 +6614,14 @@ static void gen_store_exclusive(DisasContext *s, int
rd, int rt, int rt2,
tmp = tcg_temp_new_i32();
switch (size) {
case 0:
- gen_aa32_ld8u(tmp, addr, IS_USER(s));
+ gen_aa32_ld8u(tmp, addr, MEM_INDEX(s));
break;
case 1:
- gen_aa32_ld16u(tmp, addr, IS_USER(s));
+ gen_aa32_ld16u(tmp, addr, MEM_INDEX(s));
break;
case 2:
case 3:
- gen_aa32_ld32u(tmp, addr, IS_USER(s));
+ gen_aa32_ld32u(tmp, addr, MEM_INDEX(s));
break;
default:
abort();
@@ -6628,7 +6632,7 @@ static void gen_store_exclusive(DisasContext *s, int rd,
int rt, int rt2,
TCGv_i32 tmp2 = tcg_temp_new_i32();
tcg_gen_addi_i32(tmp2, addr, 4);
tmp = tcg_temp_new_i32();
- gen_aa32_ld32u(tmp, tmp2, IS_USER(s));
+ gen_aa32_ld32u(tmp, tmp2, MEM_INDEX(s));
tcg_temp_free_i32(tmp2);
tcg_gen_brcond_i32(TCG_COND_NE, tmp, cpu_exclusive_high, fail_label);
tcg_temp_free_i32(tmp);
@@ -6636,14 +6640,14 @@ static void gen_store_exclusive(DisasContext *s, int
rd, int rt, int rt2,
tmp = load_reg(s, rt);
switch (size) {
case 0:
- gen_aa32_st8(tmp, addr, IS_USER(s));
+ gen_aa32_st8(tmp, addr, MEM_INDEX(s));
break;
case 1:
- gen_aa32_st16(tmp, addr, IS_USER(s));
+ gen_aa32_st16(tmp, addr, MEM_INDEX(s));
break;
case 2:
case 3:
- gen_aa32_st32(tmp, addr, IS_USER(s));
+ gen_aa32_st32(tmp, addr, MEM_INDEX(s));
break;
default:
abort();
@@ -6652,7 +6656,7 @@ static void gen_store_exclusive(DisasContext *s, int rd,
int rt, int rt2,
if (size == 3) {
tcg_gen_addi_i32(addr, addr, 4);
tmp = load_reg(s, rt2);
- gen_aa32_st32(tmp, addr, IS_USER(s));
+ gen_aa32_st32(tmp, addr, MEM_INDEX(s));
tcg_temp_free_i32(tmp);
}
tcg_gen_movi_i32(cpu_R[rd], 0);
@@ -6699,11 +6703,11 @@ static void gen_srs(DisasContext *s,
}
tcg_gen_addi_i32(addr, addr, offset);
tmp = load_reg(s, 14);
- gen_aa32_st32(tmp, addr, 0);
+ gen_aa32_st32(tmp, addr, MEM_INDEX(s));
tcg_temp_free_i32(tmp);
tmp = load_cpu_field(spsr);
tcg_gen_addi_i32(addr, addr, 4);
- gen_aa32_st32(tmp, addr, 0);
+ gen_aa32_st32(tmp, addr, MEM_INDEX(s));
tcg_temp_free_i32(tmp);
if (writeback) {
switch (amode) {
@@ -6849,10 +6853,10 @@ static void disas_arm_insn(CPUARMState * env,
DisasContext *s)
tcg_gen_addi_i32(addr, addr, offset);
/* Load PC into tmp and CPSR into tmp2. */
tmp = tcg_temp_new_i32();
- gen_aa32_ld32u(tmp, addr, 0);
+ gen_aa32_ld32u(tmp, addr, MEM_INDEX(s));
tcg_gen_addi_i32(addr, addr, 4);
tmp2 = tcg_temp_new_i32();
- gen_aa32_ld32u(tmp2, addr, 0);
+ gen_aa32_ld32u(tmp2, addr, MEM_INDEX(s));
if (insn & (1 << 21)) {
/* Base writeback. */
switch (i) {
@@ -7408,13 +7412,13 @@ static void disas_arm_insn(CPUARMState * env,
DisasContext *s)
tmp = tcg_temp_new_i32();
switch (op1) {
case 0: /* lda */
- gen_aa32_ld32u(tmp, addr, IS_USER(s));
+ gen_aa32_ld32u(tmp, addr, MEM_INDEX(s));
break;
case 2: /* ldab */
- gen_aa32_ld8u(tmp, addr, IS_USER(s));
+ gen_aa32_ld8u(tmp, addr, MEM_INDEX(s));
break;
case 3: /* ldah */
- gen_aa32_ld16u(tmp, addr, IS_USER(s));
+ gen_aa32_ld16u(tmp, addr, MEM_INDEX(s));
break;
default:
abort();
@@ -7425,13 +7429,13 @@ static void disas_arm_insn(CPUARMState * env,
DisasContext *s)
tmp = load_reg(s, rm);
switch (op1) {
case 0: /* stl */
- gen_aa32_st32(tmp, addr, IS_USER(s));
+ gen_aa32_st32(tmp, addr, MEM_INDEX(s));
break;
case 2: /* stlb */
- gen_aa32_st8(tmp, addr, IS_USER(s));
+ gen_aa32_st8(tmp, addr, MEM_INDEX(s));
break;
case 3: /* stlh */
- gen_aa32_st16(tmp, addr, IS_USER(s));
+ gen_aa32_st16(tmp, addr, MEM_INDEX(s));
break;
default:
abort();
@@ -7486,11 +7490,11 @@ static void disas_arm_insn(CPUARMState * env,
DisasContext *s)
tmp = load_reg(s, rm);
tmp2 = tcg_temp_new_i32();
if (insn & (1 << 22)) {
- gen_aa32_ld8u(tmp2, addr, IS_USER(s));
- gen_aa32_st8(tmp, addr, IS_USER(s));
+ gen_aa32_ld8u(tmp2, addr, MEM_INDEX(s));
+ gen_aa32_st8(tmp, addr, MEM_INDEX(s));
} else {
- gen_aa32_ld32u(tmp2, addr, IS_USER(s));
- gen_aa32_st32(tmp, addr, IS_USER(s));
+ gen_aa32_ld32u(tmp2, addr, MEM_INDEX(s));
+ gen_aa32_st32(tmp, addr, MEM_INDEX(s));
}
tcg_temp_free_i32(tmp);
tcg_temp_free_i32(addr);
@@ -7512,14 +7516,14 @@ static void disas_arm_insn(CPUARMState * env,
DisasContext *s)
tmp = tcg_temp_new_i32();
switch(sh) {
case 1:
- gen_aa32_ld16u(tmp, addr, IS_USER(s));
+ gen_aa32_ld16u(tmp, addr, MEM_INDEX(s));
break;
case 2:
- gen_aa32_ld8s(tmp, addr, IS_USER(s));
+ gen_aa32_ld8s(tmp, addr, MEM_INDEX(s));
break;
default:
case 3:
- gen_aa32_ld16s(tmp, addr, IS_USER(s));
+ gen_aa32_ld16s(tmp, addr, MEM_INDEX(s));
break;
}
load = 1;
@@ -7529,21 +7533,21 @@ static void disas_arm_insn(CPUARMState * env,
DisasContext *s)
if (sh & 1) {
/* store */
tmp = load_reg(s, rd);
- gen_aa32_st32(tmp, addr, IS_USER(s));
+ gen_aa32_st32(tmp, addr, MEM_INDEX(s));
tcg_temp_free_i32(tmp);
tcg_gen_addi_i32(addr, addr, 4);
tmp = load_reg(s, rd + 1);
- gen_aa32_st32(tmp, addr, IS_USER(s));
+ gen_aa32_st32(tmp, addr, MEM_INDEX(s));
tcg_temp_free_i32(tmp);
load = 0;
} else {
/* load */
tmp = tcg_temp_new_i32();
- gen_aa32_ld32u(tmp, addr, IS_USER(s));
+ gen_aa32_ld32u(tmp, addr, MEM_INDEX(s));
store_reg(s, rd, tmp);
tcg_gen_addi_i32(addr, addr, 4);
tmp = tcg_temp_new_i32();
- gen_aa32_ld32u(tmp, addr, IS_USER(s));
+ gen_aa32_ld32u(tmp, addr, MEM_INDEX(s));
rd++;
load = 1;
}
@@ -7551,7 +7555,7 @@ static void disas_arm_insn(CPUARMState * env,
DisasContext *s)
} else {
/* store */
tmp = load_reg(s, rd);
- gen_aa32_st16(tmp, addr, IS_USER(s));
+ gen_aa32_st16(tmp, addr, MEM_INDEX(s));
tcg_temp_free_i32(tmp);
load = 0;
}
@@ -7877,7 +7881,8 @@ static void disas_arm_insn(CPUARMState * env,
DisasContext *s)
rn = (insn >> 16) & 0xf;
rd = (insn >> 12) & 0xf;
tmp2 = load_reg(s, rn);
- i = (IS_USER(s) || (insn & 0x01200000) == 0x00200000);
+ i = (insn & 0x01200000) == 0x00200000 ?
+ MEM_INDEX_USER(s) : MEM_INDEX(s);
if (insn & (1 << 24))
gen_add_data_offset(s, insn, tmp2);
if (insn & (1 << 20)) {
@@ -7961,7 +7966,7 @@ static void disas_arm_insn(CPUARMState * env,
DisasContext *s)
if (insn & (1 << 20)) {
/* load */
tmp = tcg_temp_new_i32();
- gen_aa32_ld32u(tmp, addr, IS_USER(s));
+ gen_aa32_ld32u(tmp, addr, MEM_INDEX(s));
if (user) {
tmp2 = tcg_const_i32(i);
gen_helper_set_user_reg(cpu_env, tmp2, tmp);
@@ -7988,7 +7993,7 @@ static void disas_arm_insn(CPUARMState * env,
DisasContext *s)
} else {
tmp = load_reg(s, i);
}
- gen_aa32_st32(tmp, addr, IS_USER(s));
+ gen_aa32_st32(tmp, addr, MEM_INDEX(s));
tcg_temp_free_i32(tmp);
}
j++;
@@ -8247,20 +8252,20 @@ static int disas_thumb2_insn(CPUARMState *env,
DisasContext *s, uint16_t insn_hw
if (insn & (1 << 20)) {
/* ldrd */
tmp = tcg_temp_new_i32();
- gen_aa32_ld32u(tmp, addr, IS_USER(s));
+ gen_aa32_ld32u(tmp, addr, MEM_INDEX(s));
store_reg(s, rs, tmp);
tcg_gen_addi_i32(addr, addr, 4);
tmp = tcg_temp_new_i32();
- gen_aa32_ld32u(tmp, addr, IS_USER(s));
+ gen_aa32_ld32u(tmp, addr, MEM_INDEX(s));
store_reg(s, rd, tmp);
} else {
/* strd */
tmp = load_reg(s, rs);
- gen_aa32_st32(tmp, addr, IS_USER(s));
+ gen_aa32_st32(tmp, addr, MEM_INDEX(s));
tcg_temp_free_i32(tmp);
tcg_gen_addi_i32(addr, addr, 4);
tmp = load_reg(s, rd);
- gen_aa32_st32(tmp, addr, IS_USER(s));
+ gen_aa32_st32(tmp, addr, MEM_INDEX(s));
tcg_temp_free_i32(tmp);
}
if (insn & (1 << 21)) {
@@ -8298,11 +8303,11 @@ static int disas_thumb2_insn(CPUARMState *env,
DisasContext *s, uint16_t insn_hw
tcg_gen_add_i32(addr, addr, tmp);
tcg_temp_free_i32(tmp);
tmp = tcg_temp_new_i32();
- gen_aa32_ld16u(tmp, addr, IS_USER(s));
+ gen_aa32_ld16u(tmp, addr, MEM_INDEX(s));
} else { /* tbb */
tcg_temp_free_i32(tmp);
tmp = tcg_temp_new_i32();
- gen_aa32_ld8u(tmp, addr, IS_USER(s));
+ gen_aa32_ld8u(tmp, addr, MEM_INDEX(s));
}
tcg_temp_free_i32(addr);
tcg_gen_shli_i32(tmp, tmp, 1);
@@ -8339,13 +8344,13 @@ static int disas_thumb2_insn(CPUARMState *env,
DisasContext *s, uint16_t insn_hw
tmp = tcg_temp_new_i32();
switch (op) {
case 0: /* ldab */
- gen_aa32_ld8u(tmp, addr, IS_USER(s));
+ gen_aa32_ld8u(tmp, addr, MEM_INDEX(s));
break;
case 1: /* ldah */
- gen_aa32_ld16u(tmp, addr, IS_USER(s));
+ gen_aa32_ld16u(tmp, addr, MEM_INDEX(s));
break;
case 2: /* lda */
- gen_aa32_ld32u(tmp, addr, IS_USER(s));
+ gen_aa32_ld32u(tmp, addr, MEM_INDEX(s));
break;
default:
abort();
@@ -8355,13 +8360,13 @@ static int disas_thumb2_insn(CPUARMState *env,
DisasContext *s, uint16_t insn_hw
tmp = load_reg(s, rs);
switch (op) {
case 0: /* stlb */
- gen_aa32_st8(tmp, addr, IS_USER(s));
+ gen_aa32_st8(tmp, addr, MEM_INDEX(s));
break;
case 1: /* stlh */
- gen_aa32_st16(tmp, addr, IS_USER(s));
+ gen_aa32_st16(tmp, addr, MEM_INDEX(s));
break;
case 2: /* stl */
- gen_aa32_st32(tmp, addr, IS_USER(s));
+ gen_aa32_st32(tmp, addr, MEM_INDEX(s));
break;
default:
abort();
@@ -8389,10 +8394,10 @@ static int disas_thumb2_insn(CPUARMState *env,
DisasContext *s, uint16_t insn_hw
tcg_gen_addi_i32(addr, addr, -8);
/* Load PC into tmp and CPSR into tmp2. */
tmp = tcg_temp_new_i32();
- gen_aa32_ld32u(tmp, addr, 0);
+ gen_aa32_ld32u(tmp, addr, MEM_INDEX(s));
tcg_gen_addi_i32(addr, addr, 4);
tmp2 = tcg_temp_new_i32();
- gen_aa32_ld32u(tmp2, addr, 0);
+ gen_aa32_ld32u(tmp2, addr, MEM_INDEX(s));
if (insn & (1 << 21)) {
/* Base writeback. */
if (insn & (1 << 24)) {
@@ -8431,7 +8436,7 @@ static int disas_thumb2_insn(CPUARMState *env,
DisasContext *s, uint16_t insn_hw
if (insn & (1 << 20)) {
/* Load. */
tmp = tcg_temp_new_i32();
- gen_aa32_ld32u(tmp, addr, IS_USER(s));
+ gen_aa32_ld32u(tmp, addr, MEM_INDEX(s));
if (i == 15) {
gen_bx(s, tmp);
} else if (i == rn) {
@@ -8443,7 +8448,7 @@ static int disas_thumb2_insn(CPUARMState *env,
DisasContext *s, uint16_t insn_hw
} else {
/* Store. */
tmp = load_reg(s, i);
- gen_aa32_st32(tmp, addr, IS_USER(s));
+ gen_aa32_st32(tmp, addr, MEM_INDEX(s));
tcg_temp_free_i32(tmp);
}
tcg_gen_addi_i32(addr, addr, 4);
@@ -9113,7 +9118,7 @@ static int disas_thumb2_insn(CPUARMState *env,
DisasContext *s, uint16_t insn_hw
{
int postinc = 0;
int writeback = 0;
- int user;
+ int mem_idx;
if ((insn & 0x01100000) == 0x01000000) {
if (disas_neon_ls_insn(env, s, insn))
goto illegal_op;
@@ -9157,7 +9162,7 @@ static int disas_thumb2_insn(CPUARMState *env,
DisasContext *s, uint16_t insn_hw
return 1;
}
}
- user = IS_USER(s);
+ mem_idx = MEM_INDEX(s);
if (rn == 15) {
addr = tcg_temp_new_i32();
/* PC relative. */
@@ -9194,7 +9199,7 @@ static int disas_thumb2_insn(CPUARMState *env,
DisasContext *s, uint16_t insn_hw
break;
case 0xe: /* User privilege. */
tcg_gen_addi_i32(addr, addr, imm);
- user = 1;
+ mem_idx = MEM_INDEX_USER(s);
break;
case 0x9: /* Post-decrement. */
imm = -imm;
@@ -9221,19 +9226,19 @@ static int disas_thumb2_insn(CPUARMState *env,
DisasContext *s, uint16_t insn_hw
tmp = tcg_temp_new_i32();
switch (op) {
case 0:
- gen_aa32_ld8u(tmp, addr, user);
+ gen_aa32_ld8u(tmp, addr, mem_idx);
break;
case 4:
- gen_aa32_ld8s(tmp, addr, user);
+ gen_aa32_ld8s(tmp, addr, mem_idx);
break;
case 1:
- gen_aa32_ld16u(tmp, addr, user);
+ gen_aa32_ld16u(tmp, addr, mem_idx);
break;
case 5:
- gen_aa32_ld16s(tmp, addr, user);
+ gen_aa32_ld16s(tmp, addr, mem_idx);
break;
case 2:
- gen_aa32_ld32u(tmp, addr, user);
+ gen_aa32_ld32u(tmp, addr, mem_idx);
break;
default:
tcg_temp_free_i32(tmp);
@@ -9250,13 +9255,13 @@ static int disas_thumb2_insn(CPUARMState *env,
DisasContext *s, uint16_t insn_hw
tmp = load_reg(s, rs);
switch (op) {
case 0:
- gen_aa32_st8(tmp, addr, user);
+ gen_aa32_st8(tmp, addr, mem_idx);
break;
case 1:
- gen_aa32_st16(tmp, addr, user);
+ gen_aa32_st16(tmp, addr, mem_idx);
break;
case 2:
- gen_aa32_st32(tmp, addr, user);
+ gen_aa32_st32(tmp, addr, mem_idx);
break;
default:
tcg_temp_free_i32(tmp);
@@ -9393,7 +9398,7 @@ static void disas_thumb_insn(CPUARMState *env,
DisasContext *s)
addr = tcg_temp_new_i32();
tcg_gen_movi_i32(addr, val);
tmp = tcg_temp_new_i32();
- gen_aa32_ld32u(tmp, addr, IS_USER(s));
+ gen_aa32_ld32u(tmp, addr, MEM_INDEX(s));
tcg_temp_free_i32(addr);
store_reg(s, rd, tmp);
break;
@@ -9596,28 +9601,28 @@ static void disas_thumb_insn(CPUARMState *env,
DisasContext *s)
switch (op) {
case 0: /* str */
- gen_aa32_st32(tmp, addr, IS_USER(s));
+ gen_aa32_st32(tmp, addr, MEM_INDEX(s));
break;
case 1: /* strh */
- gen_aa32_st16(tmp, addr, IS_USER(s));
+ gen_aa32_st16(tmp, addr, MEM_INDEX(s));
break;
case 2: /* strb */
- gen_aa32_st8(tmp, addr, IS_USER(s));
+ gen_aa32_st8(tmp, addr, MEM_INDEX(s));
break;
case 3: /* ldrsb */
- gen_aa32_ld8s(tmp, addr, IS_USER(s));
+ gen_aa32_ld8s(tmp, addr, MEM_INDEX(s));
break;
case 4: /* ldr */
- gen_aa32_ld32u(tmp, addr, IS_USER(s));
+ gen_aa32_ld32u(tmp, addr, MEM_INDEX(s));
break;
case 5: /* ldrh */
- gen_aa32_ld16u(tmp, addr, IS_USER(s));
+ gen_aa32_ld16u(tmp, addr, MEM_INDEX(s));
break;
case 6: /* ldrb */
- gen_aa32_ld8u(tmp, addr, IS_USER(s));
+ gen_aa32_ld8u(tmp, addr, MEM_INDEX(s));
break;
case 7: /* ldrsh */
- gen_aa32_ld16s(tmp, addr, IS_USER(s));
+ gen_aa32_ld16s(tmp, addr, MEM_INDEX(s));
break;
}
if (op >= 3) { /* load */
@@ -9639,12 +9644,12 @@ static void disas_thumb_insn(CPUARMState *env,
DisasContext *s)
if (insn & (1 << 11)) {
/* load */
tmp = tcg_temp_new_i32();
- gen_aa32_ld32u(tmp, addr, IS_USER(s));
+ gen_aa32_ld32u(tmp, addr, MEM_INDEX(s));
store_reg(s, rd, tmp);
} else {
/* store */
tmp = load_reg(s, rd);
- gen_aa32_st32(tmp, addr, IS_USER(s));
+ gen_aa32_st32(tmp, addr, MEM_INDEX(s));
tcg_temp_free_i32(tmp);
}
tcg_temp_free_i32(addr);
@@ -9661,12 +9666,12 @@ static void disas_thumb_insn(CPUARMState *env,
DisasContext *s)
if (insn & (1 << 11)) {
/* load */
tmp = tcg_temp_new_i32();
- gen_aa32_ld8u(tmp, addr, IS_USER(s));
+ gen_aa32_ld8u(tmp, addr, MEM_INDEX(s));
store_reg(s, rd, tmp);
} else {
/* store */
tmp = load_reg(s, rd);
- gen_aa32_st8(tmp, addr, IS_USER(s));
+ gen_aa32_st8(tmp, addr, MEM_INDEX(s));
tcg_temp_free_i32(tmp);
}
tcg_temp_free_i32(addr);
@@ -9683,12 +9688,12 @@ static void disas_thumb_insn(CPUARMState *env,
DisasContext *s)
if (insn & (1 << 11)) {
/* load */
tmp = tcg_temp_new_i32();
- gen_aa32_ld16u(tmp, addr, IS_USER(s));
+ gen_aa32_ld16u(tmp, addr, MEM_INDEX(s));
store_reg(s, rd, tmp);
} else {
/* store */
tmp = load_reg(s, rd);
- gen_aa32_st16(tmp, addr, IS_USER(s));
+ gen_aa32_st16(tmp, addr, MEM_INDEX(s));
tcg_temp_free_i32(tmp);
}
tcg_temp_free_i32(addr);
@@ -9704,12 +9709,12 @@ static void disas_thumb_insn(CPUARMState *env,
DisasContext *s)
if (insn & (1 << 11)) {
/* load */
tmp = tcg_temp_new_i32();
- gen_aa32_ld32u(tmp, addr, IS_USER(s));
+ gen_aa32_ld32u(tmp, addr, MEM_INDEX(s));
store_reg(s, rd, tmp);
} else {
/* store */
tmp = load_reg(s, rd);
- gen_aa32_st32(tmp, addr, IS_USER(s));
+ gen_aa32_st32(tmp, addr, MEM_INDEX(s));
tcg_temp_free_i32(tmp);
}
tcg_temp_free_i32(addr);
@@ -9777,12 +9782,12 @@ static void disas_thumb_insn(CPUARMState *env,
DisasContext *s)
if (insn & (1 << 11)) {
/* pop */
tmp = tcg_temp_new_i32();
- gen_aa32_ld32u(tmp, addr, IS_USER(s));
+ gen_aa32_ld32u(tmp, addr, MEM_INDEX(s));
store_reg(s, i, tmp);
} else {
/* push */
tmp = load_reg(s, i);
- gen_aa32_st32(tmp, addr, IS_USER(s));
+ gen_aa32_st32(tmp, addr, MEM_INDEX(s));
tcg_temp_free_i32(tmp);
}
/* advance to the next address. */
@@ -9794,13 +9799,13 @@ static void disas_thumb_insn(CPUARMState *env,
DisasContext *s)
if (insn & (1 << 11)) {
/* pop pc */
tmp = tcg_temp_new_i32();
- gen_aa32_ld32u(tmp, addr, IS_USER(s));
+ gen_aa32_ld32u(tmp, addr, MEM_INDEX(s));
/* don't set the pc until the rest of the instruction
has completed */
} else {
/* push lr */
tmp = load_reg(s, 14);
- gen_aa32_st32(tmp, addr, IS_USER(s));
+ gen_aa32_st32(tmp, addr, MEM_INDEX(s));
tcg_temp_free_i32(tmp);
}
tcg_gen_addi_i32(addr, addr, 4);
@@ -9926,7 +9931,7 @@ static void disas_thumb_insn(CPUARMState *env,
DisasContext *s)
if (insn & (1 << 11)) {
/* load */
tmp = tcg_temp_new_i32();
- gen_aa32_ld32u(tmp, addr, IS_USER(s));
+ gen_aa32_ld32u(tmp, addr, MEM_INDEX(s));
if (i == rn) {
loaded_var = tmp;
} else {
@@ -9935,7 +9940,7 @@ static void disas_thumb_insn(CPUARMState *env,
DisasContext *s)
} else {
/* store */
tmp = load_reg(s, i);
- gen_aa32_st32(tmp, addr, IS_USER(s));
+ gen_aa32_st32(tmp, addr, MEM_INDEX(s));
tcg_temp_free_i32(tmp);
}
/* advance to the next address */
@@ -10056,6 +10061,8 @@ static inline void
gen_intermediate_code_internal(ARMCPU *cpu,
#if !defined(CONFIG_USER_ONLY)
dc->user = (ARM_TBFLAG_PRIV(tb->flags) == 0);
dc->ns = ARM_TBFLAG_NS(tb->flags);
+ dc->mem_idx = (IS_USER(dc) ? MMU_USER_BIT : 0) |
+ (IS_NS(dc) ? MMU_NS_BIT : 0);
#endif
dc->vfp_enabled = ARM_TBFLAG_VFPEN(tb->flags);
dc->vec_len = ARM_TBFLAG_VECLEN(tb->flags);
diff --git a/target-arm/translate.h b/target-arm/translate.h
index 05b4f34..be974e3 100644
--- a/target-arm/translate.h
+++ b/target-arm/translate.h
@@ -20,6 +20,7 @@ typedef struct DisasContext {
#if !defined(CONFIG_USER_ONLY)
int user;
int ns;
+ int mem_idx;
#endif
int vfp_enabled;
int vec_len;
--
1.7.9.5
- Re: [Qemu-devel] [RFC PATCH 04/21] target-arm: preserve RAO/WI bits of ARMv7 SCTLR, (continued)
[Qemu-devel] [RFC PATCH 10/21] target-arm: add non-secure Translation Block flag, Sergey Fedorov, 2013/12/03
[Qemu-devel] [RFC PATCH 03/21] target-arm: adjust TTBCR for TrustZone feature, Sergey Fedorov, 2013/12/03
[Qemu-devel] [RFC PATCH 09/21] target-arm: adjust SCR CP15 register access rights, Sergey Fedorov, 2013/12/03
[Qemu-devel] [RFC PATCH 14/21] target-arm: split TLB for secure state,
Sergey Fedorov <=
[Qemu-devel] [RFC PATCH 08/21] target-arm: adjust arm_current_pl() for TrustZone, Sergey Fedorov, 2013/12/03
[Qemu-devel] [RFC PATCH 01/21] target-arm: add TrustZone CPU feature, Sergey Fedorov, 2013/12/03
[Qemu-devel] [RFC PATCH 05/21] target-arm: add CPU Monitor mode, Sergey Fedorov, 2013/12/03
- Re: [Qemu-devel] [RFC PATCH 05/21] target-arm: add CPU Monitor mode, Peter Crosthwaite, 2013/12/03
- Re: [Qemu-devel] [RFC PATCH 05/21] target-arm: add CPU Monitor mode, Peter Maydell, 2013/12/03
- Re: [Qemu-devel] [RFC PATCH 05/21] target-arm: add CPU Monitor mode, Fedorov Sergey, 2013/12/04
- Re: [Qemu-devel] [RFC PATCH 05/21] target-arm: add CPU Monitor mode, Peter Crosthwaite, 2013/12/04
- Re: [Qemu-devel] [RFC PATCH 05/21] target-arm: add CPU Monitor mode, Peter Maydell, 2013/12/04
- Re: [Qemu-devel] [RFC PATCH 05/21] target-arm: add CPU Monitor mode, Fedorov Sergey, 2013/12/04