Re: [Qemu-devel] KVM guest cpu L3 cache and cpufreq

[Eduardo Habkost]

On Mon, Aug 26, 2013 at 06:45:27PM +0200, Benoît Canet wrote:
> > Talk to Eduardo since this is related to cpuid configuration and he is
> > an expert.
> 
> I found the following in target-i386/cpu.c
> 
>     case 0x80000006:
>         /* cache info (L2 cache) */
>         *eax = 0;
>         *ebx = 0x42004200;
>         *ecx = 0x02008140;
>         *edx = 0;
>         break;
> 
> From the AMD cpuid book it look like the L3 settings are not defined (edx).
> 
> Eduardo: A user I know want to be able to set the size of the guest L3 cache.
> I am ok to write a patch to do so.
> 
> Do you have some recommandations regarding the other fields of the edx 
> register ?

Probably it will be a good idea to let each CPU model have their own
defaults for the cache information.

> What would be an acceptable user interface to set this ?

Things I can remember from the top of my head:

 * It would be interesting to redo this patch, before doing anything else:
   
https://github.com/ehabkost/qemu-hacks/commit/10b675fa1269a65a553586545fdbcd95ace79d65
 * We need to keep compatibility on existing machine-types (not change
   the cache size);
 * If some information is reported on multiple CPUID leaves, we need to
   keep them consistent with each other (see the FIXME comments on the
   URL above);
 * Please use QOM properties to allow the cache sizes/topologies to be set.

-- 
Eduardo