[Qemu-devel] [PATCH 1/2] ich9: update sci on gpe write

[Hu Tao]

OSPM may disable the sci by clearing GPEx_BLK EN bit, in the case
we have to set sci level to 0 or guest will receive sci interrupts
endlessly.

Signed-off-by: Hu Tao <address@hidden>
---
 hw/acpi/ich9.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/hw/acpi/ich9.c b/hw/acpi/ich9.c
index 3fb443d..8717c15 100644
--- a/hw/acpi/ich9.c
+++ b/hw/acpi/ich9.c
@@ -79,6 +79,8 @@ static void ich9_gpe_writeb(void *opaque, hwaddr addr, 
uint64_t val,
 {
     ICH9LPCPMRegs *pm = opaque;
     acpi_gpe_ioport_writeb(&pm->acpi_regs, addr, val);
+
+    pm_update_sci(pm);
 }
 
 static const MemoryRegionOps ich9_gpe_ops = {
-- 
1.8.1.4