Re: [Qemu-devel] [PATCH v3] PIIX3: reset the VM when the Reset Control Register's RCPU bit gets set

[Michael S. Tsirkin]

On Tue, Feb 19, 2013 at 04:45:52PM +0100, Laszlo Ersek wrote:
> On 02/19/13 16:15, Michael S. Tsirkin wrote:
> > On Tue, Feb 19, 2013 at 03:57:19PM +0100, Laszlo Ersek wrote:
> 
> >> ... earlier Michael pointed out to me that a shared handler for the
> >> [0xcf8, 0xcfc) range would be preferred over the overlapping regions.
> >> (Which makes me recall my RFC version of the patch.) Since RST_CNT on
> >> the ICH9 is also at 0xcf9, I assume I should fix up the PIIX3 first and
> >> then follow the PIIX3 impl. in ICH9.
> 
> > Yes I think it's the cleanest way to do this.
> > Though, it was Blue Swirl that pushed for the separate handlers right?
> 
> Yes I think it was his recommendation:
> http://thread.gmane.org/gmane.comp.emulators.qemu/187502/focus=187736
> http://thread.gmane.org/gmane.comp.emulators.qemu/187502/focus=188318
> 
> > I'm not too picky, separate handlers seem to work ATM
> > even though I think it's more a bug than a feature.
> 
> OK, then I'll assume you're not going to NAK the ICH9 patch (to be
> written) just because of its use of overlapping regions (if it works at
> all of course).
> 
> Thanks!
> Laszlo

Yea, I don't mind.