Re: [Qemu-devel] qemu physical address

[Blue Swirl]

On Thu, Apr 19, 2012 at 01:55, Xin Tong <address@hidden> wrote:
> but should not the address be within 1 - 4G-1 even with PAE. is not
> the PAE just using 64bits addresses as supposed to 32 bit ? what does
> the physical address bigger than 4G mean ?  is not the physical
> address starting from 0 from the prospective of the processor ?

With 64 bit physical addresses the range can be 0 to
0xffffffffffffffff. Perhaps you need to read more background material,
for example Intel or AMD processor manuals are quite extensive.

Please don't top post, it breaks the natural reply order.

>
> Xin
>
>
> On Wed, Apr 18, 2012 at 4:03 PM, Blue Swirl <address@hidden> wrote:
>> On Wed, Apr 18, 2012 at 01:28, Xin Tong <address@hidden> wrote:
>>> I am reading how qemu refill TLB working.
>>>
>>> target-i386/helper.c
>>>
>>>    pte = pte & env->a20_mask;
>>>
>>>    /* Even if 4MB pages, we map only one 4KB page in the cache to
>>>       avoid filling it too fast */
>>>    page_offset = (addr & TARGET_PAGE_MASK) & (page_size - 1);
>>>    paddr = (pte & TARGET_PAGE_MASK) + page_offset;
>>>    vaddr = virt_addr + page_offset;
>>>
>>>
>>> How can the paddr be bigger than 4G even though i gave the machine
>>> 4096 MB of memory ( i.e. qemu -m 4096 ...). should not paddr be within
>>> 0 - 4G-1 ?
>>
>> No. There's PAE and the same code is used by both i386 and x86_64.
>>
>>>
>>> Thanks
>>>
>>> Xin
>>>