[Qemu-devel] [PATCH 07/40] Add GEN_VXRFORM{, 1} macros for subsequent instructions.

[Nathan Froyd]

Signed-off-by: Nathan Froyd <address@hidden>
---
 target-ppc/translate.c |   27 +++++++++++++++++++++++++++
 1 files changed, 27 insertions(+), 0 deletions(-)

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 56d5c51..967d9da 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6206,6 +6206,33 @@ GEN_VXFORM(vavgsb, 1, 20);
 GEN_VXFORM(vavgsh, 1, 21);
 GEN_VXFORM(vavgsw, 1, 22);
 
+#define GEN_VXRFORM1(opname, name, str, opc2, opc3)                     \
+    GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC)   \
+    {                                                                   \
+        TCGv_ptr ra, rb, rd;                                            \
+        TCGv_i32 result;                                                \
+        if (unlikely(!ctx->altivec_enabled)) {                          \
+            gen_exception(ctx, POWERPC_EXCP_VPU);                       \
+            return;                                                     \
+        }                                                               \
+        ra = gen_avr_ptr(rA(ctx->opcode));                              \
+        rb = gen_avr_ptr(rB(ctx->opcode));                              \
+        rd = gen_avr_ptr(rD(ctx->opcode));                              \
+        result = tcg_temp_new_i32();                                    \
+        gen_helper_##opname (result, rd, ra, rb);                       \
+        if (opc3 & 0x1) {                                               \
+            tcg_gen_mov_i32(cpu_crf[6], result);                        \
+        }                                                               \
+        tcg_temp_free_ptr(ra);                                          \
+        tcg_temp_free_ptr(rb);                                          \
+        tcg_temp_free_ptr(rd);                                          \
+        tcg_temp_free_i32(result);                                      \
+    }
+
+#define GEN_VXRFORM(name, opc2, opc3)                                \
+    GEN_VXRFORM1(name, name, #name, opc2, opc3)                      \
+    GEN_VXRFORM1(name, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
+
 /***                           SPE extension                               ***/
 /* Register moves */
 
-- 
1.6.0.5