[Qemu-devel] [PATCH] add SuperSPARC breakpoint registers

[Robert Reif]

Index: target-sparc/cpu.h
===================================================================
--- target-sparc/cpu.h  (revision 6121)
+++ target-sparc/cpu.h  (working copy)
@@ -300,6 +301,7 @@
     uint32_t mmuregs[32];
     uint64_t mxccdata[4];
     uint64_t mxccregs[8];
+    uint64_t mmubpregs[4];
     uint64_t prom_addr;
 #endif
     /* temporary float registers */
Index: target-sparc/op_helper.c
===================================================================
--- target-sparc/op_helper.c    (revision 6121)
+++ target-sparc/op_helper.c    (working copy)
@@ -953,6 +953,28 @@
     case 0x39: /* data cache diagnostic register */
         ret = 0;
         break;
+    case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */
+        {
+            int reg = (addr >> 8) & 3;
+
+            switch(reg) {
+            case 0: /* Breakpoint Value (Addr) */
+                ret = env->mmubpregs[reg];
+                break;
+            case 1: /* Breakpoint Mask */
+                ret = env->mmubpregs[reg];
+                break;
+            case 2: /* Breakpoint Control */
+                ret = env->mmubpregs[reg];
+                break;
+            case 3: /* Breakpoint Status */
+                ret = env->mmubpregs[reg];
+                env->mmubpregs[reg] = 0ULL;
+                break;
+            }
+            DPRINTF_MMU("read breakpoint reg[%d] 0x%016llx\n", reg, ret);
+        }
+        break;
     case 8: /* User code access, XXX */
     default:
         do_unassigned_access(addr, 0, 0, asi, size);
@@ -1283,9 +1305,30 @@
                // descriptor diagnostic
     case 0x36: /* I-cache flash clear */
     case 0x37: /* D-cache flash clear */
-    case 0x38: /* breakpoint diagnostics */
     case 0x4c: /* breakpoint action */
         break;
+    case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/
+        {
+            int reg = (addr >> 8) & 3;
+
+            switch(reg) {
+            case 0: /* Breakpoint Value (Addr) */
+                env->mmubpregs[reg] = (val & 0xfffffffffULL);
+                break;
+            case 1: /* Breakpoint Mask */
+                env->mmubpregs[reg] = (val & 0xfffffffffULL);
+                break;
+            case 2: /* Breakpoint Control */
+                env->mmubpregs[reg] = (val & 0x7fULL);
+                break;
+            case 3: /* Breakpoint Status */
+                env->mmubpregs[reg] = (val & 0xfULL);
+                break;
+            }
+            DPRINTF_MMU("write breakpoint reg[%d] 0x%016llx\n", reg,
+                        env->mmuregs[reg]);
+        }
+        break;
     case 8: /* User code access, XXX */
     case 9: /* Supervisor code access, XXX */
     default: