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[Qemu-devel] [6092] PCI: Mask writes to RO bits in the command reg of PC
From: |
Aurelien Jarno |
Subject: |
[Qemu-devel] [6092] PCI: Mask writes to RO bits in the command reg of PCI config space |
Date: |
Thu, 18 Dec 2008 22:43:41 +0000 |
Revision: 6092
http://svn.sv.gnu.org/viewvc/?view=rev&root=qemu&revision=6092
Author: aurel32
Date: 2008-12-18 22:43:40 +0000 (Thu, 18 Dec 2008)
Log Message:
-----------
PCI: Mask writes to RO bits in the command reg of PCI config space
The Command register in the PCI config space has some read-only bits.
Any writes to those bits should be masked out.
Signed-off-by: Amit Shah <address@hidden>
Signed-off-by: Aurelien Jarno <address@hidden>
Modified Paths:
--------------
trunk/hw/pci.c
trunk/hw/pci.h
Modified: trunk/hw/pci.c
===================================================================
--- trunk/hw/pci.c 2008-12-18 22:43:33 UTC (rev 6091)
+++ trunk/hw/pci.c 2008-12-18 22:43:40 UTC (rev 6092)
@@ -417,6 +417,9 @@
if (can_write) {
/* Mask out writes to reserved bits in registers */
switch (addr) {
+ case 0x05:
+ val &= ~PCI_COMMAND_RESERVED_MASK_HI;
+ break;
case 0x06:
val &= ~PCI_STATUS_RESERVED_MASK_LO;
break;
Modified: trunk/hw/pci.h
===================================================================
--- trunk/hw/pci.h 2008-12-18 22:43:33 UTC (rev 6091)
+++ trunk/hw/pci.h 2008-12-18 22:43:40 UTC (rev 6092)
@@ -69,6 +69,11 @@
#define PCI_STATUS_RESERVED_MASK_HI (PCI_STATUS_DEVSEL >> 8)
+/* Bits in the PCI Command Register (PCI 2.3 spec) */
+#define PCI_COMMAND_RESERVED 0xf800
+
+#define PCI_COMMAND_RESERVED_MASK_HI (PCI_COMMAND_RESERVED >> 8)
+
struct PCIDevice {
/* PCI config space */
uint8_t config[256];
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