[Qemu-devel] [PATCH 18/42] target-ppc: add lvs{l,r} instructions.

[Nathan Froyd]

Signed-off-by: Nathan Froyd <address@hidden>
---
 target-ppc/helper.h    |    2 ++
 target-ppc/op_helper.c |   18 ++++++++++++++++++
 target-ppc/translate.c |   32 ++++++++++++++++++++++++++++++++
 3 files changed, 52 insertions(+), 0 deletions(-)

diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index a784fae..1d05cb2 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -159,6 +159,8 @@ DEF_HELPER_3(vslo, void, avr, avr, avr)
 DEF_HELPER_3(vsro, void, avr, avr, avr)
 DEF_HELPER_3(vaddcuw, void, avr, avr, avr)
 DEF_HELPER_3(vsubcuw, void, avr, avr, avr)
+DEF_HELPER_2(lvsl, void, avr, tl);
+DEF_HELPER_2(lvsr, void, avr, tl);
 
 DEF_HELPER_1(efscfsi, i32, i32)
 DEF_HELPER_1(efscfui, i32, i32)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index 1a94735..d453a41 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -2033,6 +2033,24 @@ target_ulong helper_dlmzb (target_ulong high, 
target_ulong low, uint32_t update_
   for (index = N_ELEMS(element)-1; index >= 0; index--)
 #endif
 
+void helper_lvsl (ppc_avr_t *r, target_ulong sh)
+{
+    int i, j = (sh & 0xf);
+
+    VECTOR_FOR_INORDER_I (i, u8) {
+        r->u8[i] = j++;
+    }
+}
+
+void helper_lvsr (ppc_avr_t *r, target_ulong sh)
+{
+    int i, j = 0x10 - (sh & 0xf);
+
+    VECTOR_FOR_INORDER_I (i, u8) {
+        r->u8[i] = j++;
+    }
+}
+
 void helper_vaddcuw (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
 {
   VECTOR_FOR(u32) {
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 05912b6..791f76b 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -6116,6 +6116,38 @@ GEN_VR_STX(svx, 0x07, 0x07);
 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
 GEN_VR_STX(svxl, 0x07, 0x0F);
 
+GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC)
+{
+    TCGv_ptr rd;
+    TCGv EA;
+    if (unlikely(!ctx->altivec_enabled)) {
+        gen_exception(ctx, POWERPC_EXCP_VPU);
+        return;
+    }
+    EA = tcg_temp_new();
+    gen_addr_reg_index(ctx, EA);
+    rd = gen_avr_ptr(rD(ctx->opcode));
+    gen_helper_lvsl(rd, EA);
+    tcg_temp_free(EA);
+    tcg_temp_free(rd);
+}
+
+GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC)
+{
+    TCGv_ptr rd;
+    TCGv EA;
+    if (unlikely(!ctx->altivec_enabled)) {
+        gen_exception(ctx, POWERPC_EXCP_VPU);
+        return;
+    }
+    EA = tcg_temp_new();
+    gen_addr_reg_index(ctx, EA);
+    rd = gen_avr_ptr(rD(ctx->opcode));
+    gen_helper_lvsr(rd, EA);
+    tcg_temp_free(EA);
+    tcg_temp_free(rd);
+}
+
 /* Logical operations */
 #define GEN_VX_LOGICAL(name, tcg_op, xo)                                \
 GEN_HANDLER(name, 0x04, (xo >> 1) & 0x1f, (xo >> 6) & 0x1f, 0x00000000, 
PPC_ALTIVEC) \
-- 
1.6.0.5