[Qemu-devel] [PATCH 5/6] PowerPC 440EP SoC emulation

[Hollis Blanchard]

Wire up the system-on-chip devices present on 440EP chips.

This patch is a little unusual in that qemu doesn't actually emulate the 440
core, but we use this board code with KVM (which does). If/when 440 core
emulation is supported, the kvm_enabled() hack can be removed.

Signed-off-by: Hollis Blanchard <address@hidden>
---
 Makefile.target |    1 +
 hw/ppc440.c     |  144 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
 hw/ppc440.h     |   20 ++++++++
 3 files changed, 165 insertions(+), 0 deletions(-)
 create mode 100644 hw/ppc440.c
 create mode 100644 hw/ppc440.h

diff --git a/Makefile.target b/Makefile.target
index 5da4994..6032af0 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -652,6 +652,7 @@ OBJS+= heathrow_pic.o grackle_pci.o ppc_oldworld.o
 OBJS+= unin_pci.o ppc_chrp.o
 # PowerPC 4xx boards
 OBJS+= pflash_cfi02.o ppc4xx_devs.o ppc4xx_pci.o ppc405_uc.o ppc405_boards.o
+OBJS+= ppc440.o
 ifdef CONFIG_KVM
 OBJS+= kvm_ppc.o
 endif
diff --git a/hw/ppc440.c b/hw/ppc440.c
new file mode 100644
index 0000000..654249f
--- /dev/null
+++ b/hw/ppc440.c
@@ -0,0 +1,144 @@
+/*
+ * Qemu PowerPC 440 chip emulation
+ *
+ * Copyright 2007 IBM Corporation.
+ * Authors:
+ *     Jerone Young <address@hidden>
+ *     Christian Ehrhardt <address@hidden>
+ *     Hollis Blanchard <address@hidden>
+ *
+ * This work is licensed under the GNU GPL license version 2 or later.
+ *
+ */
+
+#include "hw.h"
+#include "isa.h"
+#include "ppc.h"
+#include "ppc4xx.h"
+#include "ppc440.h"
+#include "ppc405.h"
+#include "sysemu.h"
+#include "kvm.h"
+
+#define PPC440EP_SDRAM_NR_BANKS 4
+
+#define PPC440EP_PCI_CONFIG     0xeec00000
+#define PPC440EP_PCI_INTACK     0xeed00000
+#define PPC440EP_PCI_SPECIAL    0xeed00000
+#define PPC440EP_PCI_REGS       0xef400000
+#define PPC440EP_PCI_IO         0xe8000000
+#define PPC440EP_PCI_IOLEN      0x00010000
+
+static const unsigned int ppc440ep_sdram_bank_sizes[] = {
+    256<<20, 128<<20, 64<<20, 32<<20, 16<<20, 8<<20, 0
+};
+
+/* XXX move to ppc4xx_devs.c */
+/* Fill in consecutive SDRAM banks with 'ram_size' bytes of memory.
+ *
+ * The SDRAM controller supports a small number of banks, and each bank must be
+ * one of a small set of sizes. The number of banks and the supported sizes
+ * varies by SoC. */
+ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks,
+                               target_phys_addr_t ram_bases[],
+                               target_phys_addr_t ram_sizes[],
+                               const unsigned int sdram_bank_sizes[])
+{
+    ram_addr_t ram_end = 0;
+    int i;
+    int j;
+
+    for (i = 0; i < nr_banks; i++) {
+        for (j = 0; sdram_bank_sizes[j] != 0; j++) {
+            unsigned int bank_size = sdram_bank_sizes[j];
+
+            if (bank_size <= ram_size) {
+                ram_bases[i] = ram_end;
+                ram_sizes[i] = bank_size;
+                ram_end += bank_size;
+                ram_size -= bank_size;
+                break;
+            }
+        }
+
+        if (!ram_size) {
+            /* No need to use the remaining banks. */
+            break;
+        }
+    }
+
+    if (ram_size)
+        printf("Truncating memory to %d MiB to fit SDRAM controller limits.\n",
+               (int)(ram_end >> 20));
+
+    return ram_end;
+}
+
+CPUState *ppc440ep_init(ram_addr_t *ram_size, PCIBus **pcip,
+                        const unsigned int pci_irq_nrs[4], int do_init)
+{
+    target_phys_addr_t ram_bases[PPC440EP_SDRAM_NR_BANKS];
+    target_phys_addr_t ram_sizes[PPC440EP_SDRAM_NR_BANKS];
+    CPUState *env;
+    ppc4xx_mmio_t *mmio;
+    qemu_irq *pic;
+    qemu_irq *irqs;
+    qemu_irq *pci_irqs;
+
+    env = cpu_ppc_init("440EP");
+    if (!env && kvm_enabled()) {
+        /* XXX Since qemu doesn't yet emulate 440, we just say it's a 405.
+         * Since KVM doesn't use qemu's CPU emulation it seems to be working
+         * OK. */
+        env = cpu_ppc_init("405");
+    }
+    if (!env) {
+        fprintf(stderr, "Unable to initialize CPU!\n");
+        exit(1);
+    }
+
+    ppc_dcr_init(env, NULL, NULL);
+
+    /* interrupt controller */
+    irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
+    irqs[PPCUIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
+    irqs[PPCUIC_OUTPUT_CINT] = ((qemu_irq 
*)env->irq_inputs)[PPC40x_INPUT_CINT];
+    pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
+
+    /* SDRAM controller */
+    memset(ram_bases, 0, sizeof(ram_bases));
+    memset(ram_sizes, 0, sizeof(ram_sizes));
+    *ram_size = ppc4xx_sdram_adjust(*ram_size, PPC440EP_SDRAM_NR_BANKS,
+                                    ram_bases, ram_sizes,
+                                    ppc440ep_sdram_bank_sizes);
+    /* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */
+    ppc405_sdram_init(env, pic[14], PPC440EP_SDRAM_NR_BANKS, ram_bases,
+                      ram_sizes, do_init);
+
+    /* PCI */
+    pci_irqs = qemu_malloc(sizeof(qemu_irq) * 4);
+    pci_irqs[0] = pic[pci_irq_nrs[0]];
+    pci_irqs[1] = pic[pci_irq_nrs[1]];
+    pci_irqs[2] = pic[pci_irq_nrs[2]];
+    pci_irqs[3] = pic[pci_irq_nrs[3]];
+    *pcip = ppc4xx_pci_init(env, pci_irqs,
+                            PPC440EP_PCI_CONFIG,
+                            PPC440EP_PCI_INTACK,
+                            PPC440EP_PCI_SPECIAL,
+                            PPC440EP_PCI_REGS);
+    if (!*pcip)
+        printf("couldn't create PCI controller!\n");
+
+    isa_mmio_init(PPC440EP_PCI_IO, PPC440EP_PCI_IOLEN);
+
+    /* MMIO -- most "miscellaneous" devices live above 0xef600000. */
+    mmio = ppc4xx_mmio_init(env, 0xef600000);
+
+    if (serial_hds[0])
+        ppc405_serial_init(env, mmio, 0x300, pic[0], serial_hds[0]);
+
+    if (serial_hds[1])
+        ppc405_serial_init(env, mmio, 0x400, pic[1], serial_hds[1]);
+
+    return env;
+}
diff --git a/hw/ppc440.h b/hw/ppc440.h
new file mode 100644
index 0000000..b6843eb
--- /dev/null
+++ b/hw/ppc440.h
@@ -0,0 +1,20 @@
+/*
+ * Qemu PowerPC 440 board emualtion
+ *
+ * Copyright 2007 IBM Corporation.
+ * Authors: Jerone Young <address@hidden>
+ *         Christian Ehrhardt <address@hidden>
+ *
+ * This work is licensed under the GNU GPL licence version 2 or later
+ *
+ */
+
+#ifndef QEMU_PPC440_H
+#define QEMU_PPC440_H
+
+#include "hw.h"
+
+CPUState *ppc440ep_init(ram_addr_t *ram_size, PCIBus **pcip,
+                        const unsigned int pci_irq_nrs[4], int do_init);
+
+#endif
-- 
1.5.6.5