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[Qemu-commits] [qemu/qemu] f65f3e: disas/riscv: Guard dec->cfg dereferen
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From: |
stefanhaRH |
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Subject: |
[Qemu-commits] [qemu/qemu] f65f3e: disas/riscv: Guard dec->cfg dereference for host d... |
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Date: |
Wed, 22 Jan 2025 04:43:29 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: f65f3ebfaddbbf679c01534d55600525a3cb330c
https://github.com/qemu/qemu/commit/f65f3ebfaddbbf679c01534d55600525a3cb330c
Author: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
M disas/riscv.c
Log Message:
-----------
disas/riscv: Guard dec->cfg dereference for host disassemble
For riscv host, it will set dec->cfg to zero. Thus we shuld guard
the dec->cfg deference for riscv host disassemble.
And in general, we should only use dec->cfg for target in three cases:
1) For not incompatible encodings, such as zcmp/zcmt/zfinx.
2) For maybe-ops encodings, they are better to be disassembled to
the "real" extensions, such as zicfiss. The guard of dec->zimop
and dec->zcmop is for comment and avoid check for every extension
that encoded in maybe-ops area.
3) For custom encodings, we have to use dec->cfg to disassemble
custom encodings using the same encoding area.
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20241206032411.52528-1-zhiwei_liu@linux.alibaba.com>
Commit: 125f97925d69aad22cf766aa1f7eac63707800d8
https://github.com/qemu/qemu/commit/125f97925d69aad22cf766aa1f7eac63707800d8
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
M tcg/aarch64/tcg-target.c.inc
M tcg/aarch64/tcg-target.h
M tcg/arm/tcg-target.c.inc
M tcg/arm/tcg-target.h
M tcg/i386/tcg-target.c.inc
M tcg/i386/tcg-target.h
M tcg/loongarch64/tcg-target.c.inc
M tcg/loongarch64/tcg-target.h
M tcg/mips/tcg-target.c.inc
M tcg/mips/tcg-target.h
M tcg/riscv/tcg-target.c.inc
M tcg/riscv/tcg-target.h
M tcg/s390x/tcg-target.c.inc
M tcg/s390x/tcg-target.h
M tcg/sparc64/tcg-target.c.inc
M tcg/sparc64/tcg-target.h
M tcg/tci/tcg-target.c.inc
M tcg/tci/tcg-target.h
Log Message:
-----------
tcg: Move call abi parameters from tcg-target.h to tcg-target.c.inc
These defines are not required outside of tcg/tcg.c,
which includes tcg-target.c.inc before use.
Reduces the exported symbol set of tcg-target.h.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 4d8722183932d9502e405ae86b1889e1d8a475e5
https://github.com/qemu/qemu/commit/4d8722183932d9502e405ae86b1889e1d8a475e5
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
M docs/devel/tcg-ops.rst
M include/tcg/tcg.h
M tcg/optimize.c
M tcg/tcg-internal.h
M tcg/tcg-op-ldst.c
M tcg/tcg-op-vec.c
M tcg/tcg-op.c
M tcg/tcg.c
Log Message:
-----------
tcg: Replace TCGOP_VECL with TCGOP_TYPE
In the replacement, drop the TCGType - TCG_TYPE_V64 adjustment,
except for the call to tcg_out_vec_op. Pass type to tcg_gen_op[1-6],
so that all integer opcodes gain the type.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: efefb9cb89f0db957a7b9775b89dc96c28da4a40
https://github.com/qemu/qemu/commit/efefb9cb89f0db957a7b9775b89dc96c28da4a40
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
M include/tcg/tcg.h
M tcg/tcg-internal.h
Log Message:
-----------
tcg: Move tcg_op_insert_{after,before} decls to tcg-internal.h
These are not particularly useful outside of optimization passes.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: fb744ece3a782c1dbe0331f312c7ea655c14c52f
https://github.com/qemu/qemu/commit/fb744ece3a782c1dbe0331f312c7ea655c14c52f
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
M tcg/tcg.c
Log Message:
-----------
tcg: Copy TCGOP_TYPE in tcg_op_insert_{after,before}
Simplify use within the optimizers by defaulting the
new opcode to the same type as the old opcode.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 2ccf871ea5e2b9164123529ae788df5d1360e036
https://github.com/qemu/qemu/commit/2ccf871ea5e2b9164123529ae788df5d1360e036
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
M include/tcg/tcg.h
Log Message:
-----------
tcg: Add TCGOP_FLAGS
To be used by some integer operations instead of,
or in addition to, a trailing constant argument.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 771a5925e8142550d9469b1ed394b63bab021b15
https://github.com/qemu/qemu/commit/771a5925e8142550d9469b1ed394b63bab021b15
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
M include/tcg/tcg.h
M tcg/tcg.c
Log Message:
-----------
tcg: Add type and flags arguments to tcg_op_supported
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 09246b1797a739c1982353eea5272735b411645d
https://github.com/qemu/qemu/commit/09246b1797a739c1982353eea5272735b411645d
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
M target/arm/tcg/translate-sve.c
Log Message:
-----------
target/arm: Do not test TCG_TARGET_HAS_bitsel_vec
Rely on tcg-op-vec.c to expand the opcode if missing.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 3a4fb570135d334af00313755addd0fc5fdf022d
https://github.com/qemu/qemu/commit/3a4fb570135d334af00313755addd0fc5fdf022d
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
M target/arm/tcg/translate-a64.c
M target/arm/tcg/translate-sve.c
M target/arm/tcg/translate.c
Log Message:
-----------
target/arm: Use tcg_op_supported
Do not reference TCG_TARGET_HAS_* directly.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 80a3a9423a86cc5dae6c6e1794328465d105d73c
https://github.com/qemu/qemu/commit/80a3a9423a86cc5dae6c6e1794328465d105d73c
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
M target/tricore/translate.c
Log Message:
-----------
target/tricore: Use tcg_op_supported
Do not reference TCG_TARGET_HAS_* directly.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 0e4c6424d639b1e2e2b780a2692d47491b7260ae
https://github.com/qemu/qemu/commit/0e4c6424d639b1e2e2b780a2692d47491b7260ae
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
M include/tcg/tcg.h
M tcg/tcg.c
Log Message:
-----------
tcg: Add tcg_op_deposit_valid
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 20fab3c2106eafc4bb306d5d2c721fcacb5b10c6
https://github.com/qemu/qemu/commit/20fab3c2106eafc4bb306d5d2c721fcacb5b10c6
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
M target/i386/tcg/emit.c.inc
Log Message:
-----------
target/i386: Remove TCG_TARGET_extract_tl_valid
This macro is unused.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 34220513bbb88bc2fc53470a83c73c828377570f
https://github.com/qemu/qemu/commit/34220513bbb88bc2fc53470a83c73c828377570f
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
M target/i386/tcg/emit.c.inc
Log Message:
-----------
target/i386: Use tcg_op_deposit_valid
Avoid direct usage of TCG_TARGET_deposit_*_valid.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: a4ca7f4a3e2467ce8378fbf8ff2379f29a8a0724
https://github.com/qemu/qemu/commit/a4ca7f4a3e2467ce8378fbf8ff2379f29a8a0724
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
M target/i386/tcg/emit.c.inc
Log Message:
-----------
target/i386: Use tcg_op_supported
Do not reference TCG_TARGET_HAS_* directly.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: a417ef835058995d09a9d2e58c04c4bf640563e3
https://github.com/qemu/qemu/commit/a417ef835058995d09a9d2e58c04c4bf640563e3
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
M include/tcg/tcg.h
M tcg/aarch64/tcg-target.c.inc
M tcg/aarch64/tcg-target.h
M tcg/arm/tcg-target.c.inc
M tcg/arm/tcg-target.h
M tcg/i386/tcg-target.c.inc
M tcg/i386/tcg-target.h
M tcg/loongarch64/tcg-target.c.inc
M tcg/loongarch64/tcg-target.h
M tcg/mips/tcg-target.c.inc
M tcg/mips/tcg-target.h
M tcg/ppc/tcg-target.c.inc
M tcg/ppc/tcg-target.h
M tcg/riscv/tcg-target.c.inc
M tcg/riscv/tcg-target.h
M tcg/s390x/tcg-target.c.inc
M tcg/s390x/tcg-target.h
M tcg/sparc64/tcg-target.c.inc
M tcg/sparc64/tcg-target.h
R tcg/tcg-ldst.c.inc
R tcg/tcg-pool.c.inc
M tcg/tcg.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Remove TCG_TARGET_NEED_LDST_LABELS and TCG_TARGET_NEED_POOL_LABELS
Make these features unconditional, as they're used by most
tcg backends anyway. Merge tcg-ldst.c.inc and tcg-pool.c.inc
into tcg.c and mark some of the functions unused, so that
when the features are not used we won't get Werrors.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 76da0a9c83e65634cb24502e642a194177a24853
https://github.com/qemu/qemu/commit/76da0a9c83e65634cb24502e642a194177a24853
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
M include/tcg/tcg-opc.h
A tcg/aarch64/tcg-target-opc.h.inc
R tcg/aarch64/tcg-target.opc.h
A tcg/arm/tcg-target-opc.h.inc
R tcg/arm/tcg-target.opc.h
A tcg/i386/tcg-target-opc.h.inc
R tcg/i386/tcg-target.opc.h
A tcg/loongarch64/tcg-target-opc.h.inc
R tcg/loongarch64/tcg-target.opc.h
A tcg/mips/tcg-target-opc.h.inc
A tcg/ppc/tcg-target-opc.h.inc
R tcg/ppc/tcg-target.opc.h
A tcg/riscv/tcg-target-opc.h.inc
R tcg/riscv/tcg-target.opc.h
A tcg/s390x/tcg-target-opc.h.inc
R tcg/s390x/tcg-target.opc.h
A tcg/sparc64/tcg-target-opc.h.inc
A tcg/tci/tcg-target-opc.h.inc
Log Message:
-----------
tcg: Rename tcg-target.opc.h to tcg-target-opc.h.inc
In addition, add empty files for mips, sparc64 and tci.
Make the include unconditional within tcg-opc.h.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 87431dd6a94e757858d131279040aec17a444eec
https://github.com/qemu/qemu/commit/87431dd6a94e757858d131279040aec17a444eec
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
M include/tcg/tcg-opc.h
M tcg/tci/tcg-target-opc.h.inc
Log Message:
-----------
tcg/tci: Move TCI specific opcodes to tcg-target-opc.h.inc
Now that tcg-target-opc.h.inc is unconditional,
we can move these out of the generic header.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 7d3e705a96a980d80fed00de7ab4afa368a22f3f
https://github.com/qemu/qemu/commit/7d3e705a96a980d80fed00de7ab4afa368a22f3f
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
M include/tcg/tcg.h
M tcg/tcg.c
Log Message:
-----------
tcg: Move fallback tcg_can_emit_vec_op out of line
Don't reference TCG_TARGET_MAYBE_vec in a public header.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 3bff1625f7a4c2be96aedc76b270a1d67e4e6dcc
https://github.com/qemu/qemu/commit/3bff1625f7a4c2be96aedc76b270a1d67e4e6dcc
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
M tcg/ppc/tcg-target.h
Log Message:
-----------
tcg/ppc: Remove TCGPowerISA enum
Left-over from commit 623d7e3551a ("util: Add cpuinfo-ppc.c").
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20250108215156.8731-2-philmd@linaro.org>
Commit: fd4841c0433c1b433f9b3f6ddddc3e653997b26e
https://github.com/qemu/qemu/commit/fd4841c0433c1b433f9b3f6ddddc3e653997b26e
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
M include/tcg/tcg.h
A tcg/tcg-has.h
Log Message:
-----------
tcg: Extract default TCG_TARGET_HAS_foo definitions to 'tcg-has.h'
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20250108215156.8731-3-philmd@linaro.org>
Commit: e03cf27df9169867b33680261eb4162232db2cba
https://github.com/qemu/qemu/commit/e03cf27df9169867b33680261eb4162232db2cba
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
A tcg/aarch64/tcg-target-has.h
M tcg/aarch64/tcg-target.h
Log Message:
-----------
tcg/aarch64: Extract TCG_TARGET_HAS_foo defs to 'tcg-target-has.h'
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20250108215156.8731-4-philmd@linaro.org>
Commit: d3f4d0dc9cd3050f46db3e429d483cc4b3e4798d
https://github.com/qemu/qemu/commit/d3f4d0dc9cd3050f46db3e429d483cc4b3e4798d
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
A tcg/arm/tcg-target-has.h
M tcg/arm/tcg-target.h
Log Message:
-----------
tcg/arm: Extract TCG_TARGET_HAS_foo defs to 'tcg-target-has.h'
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20250108215156.8731-5-philmd@linaro.org>
Commit: 8c033f243141e9b50a93308f871f7f0b53fdc379
https://github.com/qemu/qemu/commit/8c033f243141e9b50a93308f871f7f0b53fdc379
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
A tcg/i386/tcg-target-has.h
M tcg/i386/tcg-target.h
Log Message:
-----------
tcg/i386: Extract TCG_TARGET_HAS_foo defs to 'tcg-target-has.h'
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20250108215156.8731-6-philmd@linaro.org>
Commit: 0a16d036154ecafe68db336309caed3add00fd70
https://github.com/qemu/qemu/commit/0a16d036154ecafe68db336309caed3add00fd70
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
A tcg/loongarch64/tcg-target-has.h
M tcg/loongarch64/tcg-target.h
Log Message:
-----------
tcg/loongarch64: Extract TCG_TARGET_HAS_foo defs to 'tcg-target-has.h'
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20250108215156.8731-7-philmd@linaro.org>
Commit: f975a3134d67d53e6409392e07d8cc73aebfc512
https://github.com/qemu/qemu/commit/f975a3134d67d53e6409392e07d8cc73aebfc512
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
A tcg/mips/tcg-target-has.h
M tcg/mips/tcg-target.h
Log Message:
-----------
tcg/mips: Extract TCG_TARGET_HAS_foo defs to 'tcg-target-has.h'
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20250108215156.8731-8-philmd@linaro.org>
Commit: 5f593d5b16fcbadbca8929d891a2d65144156f91
https://github.com/qemu/qemu/commit/5f593d5b16fcbadbca8929d891a2d65144156f91
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
A tcg/ppc/tcg-target-has.h
M tcg/ppc/tcg-target.h
Log Message:
-----------
tcg/ppc: Extract TCG_TARGET_HAS_foo defs to 'tcg-target-has.h'
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20250108215156.8731-9-philmd@linaro.org>
Commit: 0242532b45df877ac986b57348a536c1b76088c0
https://github.com/qemu/qemu/commit/0242532b45df877ac986b57348a536c1b76088c0
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
A tcg/riscv/tcg-target-has.h
M tcg/riscv/tcg-target.h
Log Message:
-----------
tcg/riscv: Extract TCG_TARGET_HAS_foo defs to 'tcg-target-has.h'
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20250108215156.8731-10-philmd@linaro.org>
Commit: 44c9e94bcccb6e4d7c3fb9a184830577c923907a
https://github.com/qemu/qemu/commit/44c9e94bcccb6e4d7c3fb9a184830577c923907a
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
A tcg/s390x/tcg-target-has.h
M tcg/s390x/tcg-target.h
Log Message:
-----------
tcg/s390x: Extract TCG_TARGET_HAS_foo defs to 'tcg-target-has.h'
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20250108215156.8731-11-philmd@linaro.org>
Commit: 66ba44cfbf60cb009435777a226f7c6cf248d55f
https://github.com/qemu/qemu/commit/66ba44cfbf60cb009435777a226f7c6cf248d55f
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
A tcg/sparc64/tcg-target-has.h
M tcg/sparc64/tcg-target.h
Log Message:
-----------
tcg/sparc64: Extract TCG_TARGET_HAS_foo defs to 'tcg-target-has.h'
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20250108215156.8731-12-philmd@linaro.org>
Commit: 8ae72b38b504ac450bf12025f5242cc5a4cb39b0
https://github.com/qemu/qemu/commit/8ae72b38b504ac450bf12025f5242cc5a4cb39b0
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
A tcg/tci/tcg-target-has.h
M tcg/tci/tcg-target.h
Log Message:
-----------
tcg/tci: Extract TCG_TARGET_HAS_foo defs to 'tcg-target-has.h'
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20250108215156.8731-13-philmd@linaro.org>
Commit: f15d00a4c180ffd303dc9272f34a26a185f741f8
https://github.com/qemu/qemu/commit/f15d00a4c180ffd303dc9272f34a26a185f741f8
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
M tcg/aarch64/tcg-target.h
M tcg/arm/tcg-target.h
M tcg/i386/tcg-target.h
M tcg/loongarch64/tcg-target.h
M tcg/mips/tcg-target.h
M tcg/ppc/tcg-target.h
M tcg/riscv/tcg-target.h
M tcg/s390x/tcg-target.h
M tcg/sparc64/tcg-target.h
M tcg/tcg-has.h
M tcg/tci/tcg-target.h
Log Message:
-----------
tcg: Include 'tcg-target-has.h' once in 'tcg-has.h'
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20250108215156.8731-14-philmd@linaro.org>
Commit: 93280b67381148d6b8b25f54f32901f868987c84
https://github.com/qemu/qemu/commit/93280b67381148d6b8b25f54f32901f868987c84
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
M include/tcg/tcg.h
M tcg/optimize.c
M tcg/tcg-common.c
M tcg/tcg-op-gvec.c
M tcg/tcg-op-ldst.c
M tcg/tcg-op-vec.c
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
Log Message:
-----------
tcg: Only include 'tcg-has.h' when necessary
TCG_TARGET_HAS_* definitions don't need to be exposed
by "tcg/tcg.h". Only include 'tcg-has.h' when necessary.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20250108215156.8731-15-philmd@linaro.org>
Commit: 12f06532c86467c2efac13f6cd630fa5c6f7bda8
https://github.com/qemu/qemu/commit/12f06532c86467c2efac13f6cd630fa5c6f7bda8
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
M accel/tcg/internal-target.h
A tcg/aarch64/tcg-target-mo.h
M tcg/aarch64/tcg-target.h
A tcg/arm/tcg-target-mo.h
M tcg/arm/tcg-target.h
A tcg/i386/tcg-target-mo.h
M tcg/i386/tcg-target.h
A tcg/loongarch64/tcg-target-mo.h
M tcg/loongarch64/tcg-target.h
A tcg/mips/tcg-target-mo.h
M tcg/mips/tcg-target.h
A tcg/ppc/tcg-target-mo.h
M tcg/ppc/tcg-target.h
A tcg/riscv/tcg-target-mo.h
M tcg/riscv/tcg-target.h
A tcg/s390x/tcg-target-mo.h
M tcg/s390x/tcg-target.h
A tcg/sparc64/tcg-target-mo.h
M tcg/sparc64/tcg-target.h
M tcg/tcg-op-ldst.c
A tcg/tci/tcg-target-mo.h
M tcg/tci/tcg-target.h
Log Message:
-----------
tcg: Split out tcg-target-mo.h
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: da43e5e6ba64fbe50d6437719470d57874939542
https://github.com/qemu/qemu/commit/da43e5e6ba64fbe50d6437719470d57874939542
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Use C_NotImplemented in tcg_target_op_def
Return C_NotImplemented instead of asserting for opcodes
not implemented by the backend. For now, the assertion
moves to process_op_defs.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: f44824cc4dcdc993d60639576d706ecf5996ca5a
https://github.com/qemu/qemu/commit/f44824cc4dcdc993d60639576d706ecf5996ca5a
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
M tcg/tcg.c
Log Message:
-----------
tcg: Change have_vec to has_type in tcg_op_supported
Test each vector type, not just lumping them all together.
Add tests for I32 (always true) and I64 (64-bit hosts).
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 3e80824e8bffef2d1dd27165a2cf48e8c034ed10
https://github.com/qemu/qemu/commit/3e80824e8bffef2d1dd27165a2cf48e8c034ed10
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
M include/tcg/tcg.h
M tcg/tcg.c
Log Message:
-----------
tcg: Reorg process_op_defs
Process each TCGConstraintSetIndex first. Allocate TCGArgConstraint
arrays based on those. Only afterward process the TCGOpcodes and
share those TCGArgConstraint arrays.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 501fb3da3fd60538214218cfbccc1abf45a047c2
https://github.com/qemu/qemu/commit/501fb3da3fd60538214218cfbccc1abf45a047c2
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
M include/tcg/tcg.h
M tcg/tcg-common.c
M tcg/tcg.c
Log Message:
-----------
tcg: Remove args_ct from TCGOpDef
Introduce a new function, opcode_args_ct, to look up the argument
set for an opcode. We lose the ability to assert the correctness
of the map from TCGOpcode to constraint sets at startup, but we can
still validate at runtime upon lookup.
Rename process_op_defs to process_constraint_sets, as it now does
nothing to TCGOpDef.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: ed1a653bad46752c4c4ceb2ada774dff7cd79e81
https://github.com/qemu/qemu/commit/ed1a653bad46752c4c4ceb2ada774dff7cd79e81
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
M include/tcg/tcg.h
M tcg/tcg-common.c
M tcg/tcg.c
Log Message:
-----------
tcg: Constify tcg_op_defs
Now that we're no longer assigning to TCGOpDef.args_ct,
we can make the array constant.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: b277cdd20baf6d8579aa5a874f713f9e19833c9f
https://github.com/qemu/qemu/commit/b277cdd20baf6d8579aa5a874f713f9e19833c9f
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
M tcg/tcg.c
Log Message:
-----------
tcg: Validate op supported in opcode_args_ct
We should have checked that the op is supported before
emitting it. The backend cannot be expected to have a
constraint set for unsupported ops.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 07ffd5b219681d9f6eb6bef9f66152bb88b23106
https://github.com/qemu/qemu/commit/07ffd5b219681d9f6eb6bef9f66152bb88b23106
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
M include/tcg/tcg-opc.h
M tcg/tcg.c
Log Message:
-----------
tcg: Add TCG_OPF_NOT_PRESENT to opcodes without inputs or outputs
The br, mb, goto_tb and exit_tb opcodes do not have
register operands, only constants, flags, or labels.
Remove the special case in opcode_args_ct by including
TCG_OPF_NOT_PRESENT in the flags for these opcodes.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 6323b3639cfd362abcd1f29c52455ae550d5ac99
https://github.com/qemu/qemu/commit/6323b3639cfd362abcd1f29c52455ae550d5ac99
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Pass type and flags to tcg_target_op_def
Allow the backend to make constraint choices based on more parameters.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 4e350091a2b87070967c85f9caeefeb85c4d2e8d
https://github.com/qemu/qemu/commit/4e350091a2b87070967c85f9caeefeb85c4d2e8d
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Add TCGType argument to tcg_out_op
Pass TCGOp.type to the output function.
For aarch64 and tci, use this instead of testing TCG_OPF_64BIT.
For s390x, use this instead of testing INDEX_op_deposit_i64.
For i386, use this to initialize rexw.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 931bac71fc1f877168d14e718a503c271713ed6e
https://github.com/qemu/qemu/commit/931bac71fc1f877168d14e718a503c271713ed6e
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
M include/tcg/tcg-opc.h
M include/tcg/tcg.h
Log Message:
-----------
tcg: Remove TCG_OPF_64BIT
This flag is no longer used.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 76187b4f57eb3931352e7f3e1c86d8d49545e396
https://github.com/qemu/qemu/commit/76187b4f57eb3931352e7f3e1c86d8d49545e396
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
M include/tcg/tcg-opc.h
Log Message:
-----------
tcg: Drop implementation checks from tcg-opc.h
Now that we use a functional interface to query whether the opcode
is supported, we can drop the TCG_OPF_NOT_PRESENT bit mapping from
TCG_TARGET_HAS_foo in tcg-opc.h
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: f9af66f6dc0fb5f6c570e99df318d997d5510f7f
https://github.com/qemu/qemu/commit/f9af66f6dc0fb5f6c570e99df318d997d5510f7f
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
M include/tcg/tcg-opc.h
M tcg/aarch64/tcg-target-opc.h.inc
M tcg/arm/tcg-target-opc.h.inc
M tcg/i386/tcg-target-opc.h.inc
M tcg/ppc/tcg-target-opc.h.inc
M tcg/s390x/tcg-target-opc.h.inc
Log Message:
-----------
tcg: Replace IMPLVEC with TCG_OPF_VECTOR
This is now a direct replacement.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 72912ac7365e737d9c9755437345efb47363db26
https://github.com/qemu/qemu/commit/72912ac7365e737d9c9755437345efb47363db26
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
M tcg/mips/tcg-target-has.h
Log Message:
-----------
tcg/mips: Expand bswap unconditionally
We always provide bswap subroutines, whether they are optimized
using mips32r2 when available or not.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: ad76017e51731ef84e98bd25b922fe14e656dd8d
https://github.com/qemu/qemu/commit/ad76017e51731ef84e98bd25b922fe14e656dd8d
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
M tcg/i386/tcg-target.c.inc
Log Message:
-----------
tcg/i386: Handle all 8-bit extensions for i686
When we generalize {s}extract_i32, we'll lose the
specific register constraints on ext8u and ext8s.
It's just as easy to emit a couple of insns instead.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 4bce752c1a4aad3bfba9b6447dd200fade242aed
https://github.com/qemu/qemu/commit/4bce752c1a4aad3bfba9b6447dd200fade242aed
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
M tcg/i386/tcg-target-has.h
M tcg/i386/tcg-target.c.inc
M tcg/optimize.c
M tcg/tcg-has.h
M tcg/tcg-op.c
Log Message:
-----------
tcg/i386: Fold the ext{8,16,32}[us] cases into {s}extract
Accept byte and word extensions with the extract opcodes.
This is preparatory to removing the specialized extracts.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 42ace08607669007e47d7e73aaaeb74948b0c5f2
https://github.com/qemu/qemu/commit/42ace08607669007e47d7e73aaaeb74948b0c5f2
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
M tcg/aarch64/tcg-target-has.h
Log Message:
-----------
tcg/aarch64: Provide TCG_TARGET_{s}extract_valid
Trivially mirrors TCG_TARGET_HAS_{s}extract_*.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 936fc0a96ed02e0d996ea58b05daf983b1cb3041
https://github.com/qemu/qemu/commit/936fc0a96ed02e0d996ea58b05daf983b1cb3041
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
M tcg/aarch64/tcg-target.c.inc
Log Message:
-----------
tcg/aarch64: Expand extract with offset 0 with andi
We're about to change canonicalization of masks as extract
instead of and. Retain the andi expansion here.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 802ef65b5f8dccbcabb7960bee9993ec65f95ab6
https://github.com/qemu/qemu/commit/802ef65b5f8dccbcabb7960bee9993ec65f95ab6
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
M tcg/arm/tcg-target-has.h
M tcg/arm/tcg-target.c.inc
Log Message:
-----------
tcg/arm: Add full [US]XT[BH] into {s}extract
The armv6 uxt and sxt opcodes have a 2-bit rotate field
which supports extractions from ofs = {0,8,16,24}.
Special case ofs = 0, len <= 8 as AND.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 0c44a4d3b647240aa9485e648fe5f63bed5e4820
https://github.com/qemu/qemu/commit/0c44a4d3b647240aa9485e648fe5f63bed5e4820
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
M tcg/loongarch64/tcg-target-has.h
M tcg/loongarch64/tcg-target.c.inc
Log Message:
-----------
tcg/loongarch64: Fold the ext{8,16,32}[us] cases into {s}extract
Accept byte and word extensions with the extract opcodes.
This is preparatory to removing the specialized extracts.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 791d03047bb814cc5f938f2b1f59115ef7f63344
https://github.com/qemu/qemu/commit/791d03047bb814cc5f938f2b1f59115ef7f63344
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
M tcg/mips/tcg-target-has.h
M tcg/mips/tcg-target.c.inc
Log Message:
-----------
tcg/mips: Fold the ext{8,16,32}[us] cases into {s}extract
Accept AND, ext32u, ext32s extensions with the extract opcodes.
This is preparatory to removing the specialized extracts.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 94d593941b68828a42df6d7af20fc4bb0e720df5
https://github.com/qemu/qemu/commit/94d593941b68828a42df6d7af20fc4bb0e720df5
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
M tcg/ppc/tcg-target-has.h
M tcg/ppc/tcg-target.c.inc
Log Message:
-----------
tcg/ppc: Fold the ext{8,16,32}[us] cases into {s}extract
Accept byte and word extensions with the extract opcodes.
This is preparatory to removing the specialized extracts.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 841e2c5257102c738e8578eb0ce38d3de830ea4c
https://github.com/qemu/qemu/commit/841e2c5257102c738e8578eb0ce38d3de830ea4c
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
M tcg/riscv/tcg-target-has.h
M tcg/riscv/tcg-target.c.inc
Log Message:
-----------
tcg/riscv64: Fold the ext{8,16,32}[us] cases into {s}extract
Accept byte and word extensions with the extract opcodes.
This is preparatory to removing the specialized extracts.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: fa65f13555e121566c9105f252c72a3b63f1ecea
https://github.com/qemu/qemu/commit/fa65f13555e121566c9105f252c72a3b63f1ecea
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
M tcg/riscv/tcg-target-has.h
M tcg/riscv/tcg-target.c.inc
Log Message:
-----------
tcg/riscv: Use SRAIW, SRLIW for {s}extract_i64
Extracts which abut bit 32 may use 32-bit shifts.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 42103c4ce73d7c26c48cc48f29e694700b09a937
https://github.com/qemu/qemu/commit/42103c4ce73d7c26c48cc48f29e694700b09a937
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
M tcg/s390x/tcg-target-has.h
M tcg/s390x/tcg-target.c.inc
Log Message:
-----------
tcg/s390x: Fold the ext{8,16,32}[us] cases into {s}extract
Accept byte and word extensions with the extract opcodes.
This is preparatory to removing the specialized extracts.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 3dc7e1db22b8e2f058fca36fa1ab7c78ebf1a389
https://github.com/qemu/qemu/commit/3dc7e1db22b8e2f058fca36fa1ab7c78ebf1a389
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
M tcg/sparc64/tcg-target-has.h
M tcg/sparc64/tcg-target.c.inc
Log Message:
-----------
tcg/sparc64: Use SRA, SRL for {s}extract_i64
Extracts which abut bit 32 may use 32-bit shifts.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: d9336b727ffd3430254663c8a37850242f6f07ea
https://github.com/qemu/qemu/commit/d9336b727ffd3430254663c8a37850242f6f07ea
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
M tcg/tci/tcg-target-has.h
Log Message:
-----------
tcg/tci: Provide TCG_TARGET_{s}extract_valid
Trivially mirrors TCG_TARGET_HAS_{s}extract_*.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 41736e7ce1f810594abad540c48f8390228a4d81
https://github.com/qemu/qemu/commit/41736e7ce1f810594abad540c48f8390228a4d81
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg/tci: Remove assertions for deposit and extract
We already have these assertions during opcode creation.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: c334de110ea93108feeddce11bd302146d1520f8
https://github.com/qemu/qemu/commit/c334de110ea93108feeddce11bd302146d1520f8
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
M tcg/aarch64/tcg-target-has.h
M tcg/arm/tcg-target-has.h
M tcg/i386/tcg-target-has.h
M tcg/loongarch64/tcg-target-has.h
M tcg/mips/tcg-target-has.h
M tcg/optimize.c
M tcg/ppc/tcg-target-has.h
M tcg/riscv/tcg-target-has.h
M tcg/s390x/tcg-target-has.h
M tcg/sparc64/tcg-target-has.h
M tcg/tcg-has.h
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target-has.h
Log Message:
-----------
tcg: Remove TCG_TARGET_HAS_{s}extract_{i32,i64}
Make extract and sextract "unconditional" in the sense
that the opcodes are always present. Rely instead on
TCG_TARGET_HAS_{s}extract_valid, now always defined.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 6482e9d2a40101895ae73c72466ccf4bcbee51bd
https://github.com/qemu/qemu/commit/6482e9d2a40101895ae73c72466ccf4bcbee51bd
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
M tcg/aarch64/tcg-target-has.h
M tcg/arm/tcg-target-has.h
M tcg/i386/tcg-target-has.h
M tcg/loongarch64/tcg-target-has.h
M tcg/mips/tcg-target-has.h
M tcg/ppc/tcg-target-has.h
M tcg/riscv/tcg-target-has.h
M tcg/s390x/tcg-target-has.h
M tcg/sparc64/tcg-target-has.h
M tcg/tcg-has.h
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target-has.h
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Remove TCG_TARGET_HAS_deposit_{i32,i64}
Make deposit "unconditional" in the sense that the opcode is
always present. Rely instead on TCG_TARGET_deposit_valid,
now always defined.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Commit: 2c4815590f9ea399bc87f727dd1c883b0d701bb8
https://github.com/qemu/qemu/commit/2c4815590f9ea399bc87f727dd1c883b0d701bb8
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
M host/include/riscv/host/cpuinfo.h
M util/cpuinfo-riscv.c
Log Message:
-----------
util/cpuinfo-riscv: Detect Zbs
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20250102181601.1421059-2-richard.henderson@linaro.org>
Commit: ee97eef290cde22c39b8715802bb3b0ca4555be3
https://github.com/qemu/qemu/commit/ee97eef290cde22c39b8715802bb3b0ca4555be3
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
M tcg/riscv/tcg-target-has.h
M tcg/riscv/tcg-target.c.inc
Log Message:
-----------
tcg/riscv: Use BEXTI for single-bit extractions
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20250102181601.1421059-3-richard.henderson@linaro.org>
Commit: 8095f652f237df90b7b01e025cbcebe95065541c
https://github.com/qemu/qemu/commit/8095f652f237df90b7b01e025cbcebe95065541c
Author: Helge Deller <deller@kernel.org>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
M linux-user/sparc/target_proc.h
Log Message:
-----------
linux-user: Add missing /proc/cpuinfo fields for sparc
Add some missing fields which may be parsed by userspace applications.
Signed-off-by: Helge Deller <deller@gmx.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <Z39B1wzNNpndmOxZ@p100>
Commit: d3203d5a0cff5a7064fe52b99510835e6b7eb03b
https://github.com/qemu/qemu/commit/d3203d5a0cff5a7064fe52b99510835e6b7eb03b
Author: Ilya Leoshkevich <iii@linux.ibm.com>
Date: 2025-01-17 (Fri, 17 Jan 2025)
Changed paths:
M accel/tcg/cpu-exec.c
M include/tcg/tcg.h
Log Message:
-----------
tcg: Document tb_lookup() and tcg_tb_lookup()
These similarly named functions serve different purposes; add
docstrings to highlight them.
Suggested-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20250116213214.5695-1-iii@linux.ibm.com>
Commit: 5313b1aaaccca99b2fe5a03fc6b3bfad65597b22
https://github.com/qemu/qemu/commit/5313b1aaaccca99b2fe5a03fc6b3bfad65597b22
Author: Ilya Leoshkevich <iii@linux.ibm.com>
Date: 2025-01-17 (Fri, 17 Jan 2025)
Changed paths:
M accel/tcg/translate-all.c
Log Message:
-----------
accel/tcg: Call tcg_tb_insert() for one-insn TBs
Currently one-insn TBs created from I/O memory are not added to
region_trees. Therefore, when they generate exceptions, they are not
handled by cpu_restore_state_from_tb().
For x86 this is not a problem, because x86_restore_state_to_opc() only
restores pc and cc, which already have the correct values if the first
TB instruction causes an exception. However, on several other
architectures, restore_state_to_opc() is not stricly limited to state
restoration and affects some exception-related registers, where guests
can notice incorrect values, for example:
- arm's exception.syndrome;
- hppa's unwind_breg;
- riscv's excp_uw2;
- s390x's int_pgm_ilen.
Fix by always calling tcg_tb_insert(). This may increase the size of
region_trees, but tcg_region_reset_all() clears it once code_gen_buffer
fills up, so it will not grow uncontrollably.
Do not call tb_link_page(), which would add such TBs to the QHT, to
prevent tb_lookup() from finding them. These TBs are single-use, since
subsequent reads from I/O memory may return different values; they are
not removed from code_gen_buffer only in order to keep things simple.
Co-developed-by: Nina Schoetterl-Glausch <nsg@linux.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20250116213214.5695-2-iii@linux.ibm.com>
Commit: db1649823d4f27b924a5aa5f9e0111457accb798
https://github.com/qemu/qemu/commit/db1649823d4f27b924a5aa5f9e0111457accb798
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: 2025-01-17 (Fri, 17 Jan 2025)
Changed paths:
M include/fpu/softfloat-helpers.h
Log Message:
-----------
softfloat: Constify helpers returning float_status field
These helpers don't alter float_status. Make it const.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20250116214359.67295-1-philmd@linaro.org>
Commit: 32a97c5d05c5deb54a42315d48cecf86cbeadaf4
https://github.com/qemu/qemu/commit/32a97c5d05c5deb54a42315d48cecf86cbeadaf4
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2025-01-21 (Tue, 21 Jan 2025)
Changed paths:
M accel/tcg/cpu-exec.c
M accel/tcg/internal-target.h
M accel/tcg/translate-all.c
M disas/riscv.c
M docs/devel/tcg-ops.rst
M host/include/riscv/host/cpuinfo.h
M include/fpu/softfloat-helpers.h
M include/tcg/tcg-opc.h
M include/tcg/tcg.h
M linux-user/sparc/target_proc.h
M target/arm/tcg/translate-a64.c
M target/arm/tcg/translate-sve.c
M target/arm/tcg/translate.c
M target/i386/tcg/emit.c.inc
M target/tricore/translate.c
A tcg/aarch64/tcg-target-has.h
A tcg/aarch64/tcg-target-mo.h
A tcg/aarch64/tcg-target-opc.h.inc
M tcg/aarch64/tcg-target.c.inc
M tcg/aarch64/tcg-target.h
R tcg/aarch64/tcg-target.opc.h
A tcg/arm/tcg-target-has.h
A tcg/arm/tcg-target-mo.h
A tcg/arm/tcg-target-opc.h.inc
M tcg/arm/tcg-target.c.inc
M tcg/arm/tcg-target.h
R tcg/arm/tcg-target.opc.h
A tcg/i386/tcg-target-has.h
A tcg/i386/tcg-target-mo.h
A tcg/i386/tcg-target-opc.h.inc
M tcg/i386/tcg-target.c.inc
M tcg/i386/tcg-target.h
R tcg/i386/tcg-target.opc.h
A tcg/loongarch64/tcg-target-has.h
A tcg/loongarch64/tcg-target-mo.h
A tcg/loongarch64/tcg-target-opc.h.inc
M tcg/loongarch64/tcg-target.c.inc
M tcg/loongarch64/tcg-target.h
R tcg/loongarch64/tcg-target.opc.h
A tcg/mips/tcg-target-has.h
A tcg/mips/tcg-target-mo.h
A tcg/mips/tcg-target-opc.h.inc
M tcg/mips/tcg-target.c.inc
M tcg/mips/tcg-target.h
M tcg/optimize.c
A tcg/ppc/tcg-target-has.h
A tcg/ppc/tcg-target-mo.h
A tcg/ppc/tcg-target-opc.h.inc
M tcg/ppc/tcg-target.c.inc
M tcg/ppc/tcg-target.h
R tcg/ppc/tcg-target.opc.h
A tcg/riscv/tcg-target-has.h
A tcg/riscv/tcg-target-mo.h
A tcg/riscv/tcg-target-opc.h.inc
M tcg/riscv/tcg-target.c.inc
M tcg/riscv/tcg-target.h
R tcg/riscv/tcg-target.opc.h
A tcg/s390x/tcg-target-has.h
A tcg/s390x/tcg-target-mo.h
A tcg/s390x/tcg-target-opc.h.inc
M tcg/s390x/tcg-target.c.inc
M tcg/s390x/tcg-target.h
R tcg/s390x/tcg-target.opc.h
A tcg/sparc64/tcg-target-has.h
A tcg/sparc64/tcg-target-mo.h
A tcg/sparc64/tcg-target-opc.h.inc
M tcg/sparc64/tcg-target.c.inc
M tcg/sparc64/tcg-target.h
M tcg/tcg-common.c
A tcg/tcg-has.h
M tcg/tcg-internal.h
R tcg/tcg-ldst.c.inc
M tcg/tcg-op-gvec.c
M tcg/tcg-op-ldst.c
M tcg/tcg-op-vec.c
M tcg/tcg-op.c
R tcg/tcg-pool.c.inc
M tcg/tcg.c
M tcg/tci.c
A tcg/tci/tcg-target-has.h
A tcg/tci/tcg-target-mo.h
A tcg/tci/tcg-target-opc.h.inc
M tcg/tci/tcg-target.c.inc
M tcg/tci/tcg-target.h
M util/cpuinfo-riscv.c
Log Message:
-----------
Merge tag 'pull-tcg-20250117' of https://gitlab.com/rth7680/qemu into staging
tcg:
- Add TCGOP_TYPE, TCGOP_FLAGS.
- Pass type and flags to tcg_op_supported, tcg_target_op_def.
- Split out tcg-target-has.h and unexport from tcg.h.
- Reorg constraint processing; constify TCGOpDef.
- Make extract, sextract, deposit opcodes mandatory.
- Merge ext{8,16,32}{s,u} opcodes into {s}extract.
tcg/mips: Expand bswap unconditionally
tcg/riscv: Use SRAIW, SRLIW for {s}extract_i64
tcg/riscv: Use BEXTI for single-bit extractions
tcg/sparc64: Use SRA, SRL for {s}extract_i64
disas/riscv: Guard dec->cfg dereference for host disassemble
util/cpuinfo-riscv: Detect Zbs
accel/tcg: Call tcg_tb_insert() for one-insn TBs
linux-user: Add missing /proc/cpuinfo fields for sparc
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# gpg: Signature made Fri 17 Jan 2025 13:19:33 EST
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>"
[full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* tag 'pull-tcg-20250117' of https://gitlab.com/rth7680/qemu: (68 commits)
softfloat: Constify helpers returning float_status field
accel/tcg: Call tcg_tb_insert() for one-insn TBs
tcg: Document tb_lookup() and tcg_tb_lookup()
linux-user: Add missing /proc/cpuinfo fields for sparc
tcg/riscv: Use BEXTI for single-bit extractions
util/cpuinfo-riscv: Detect Zbs
tcg: Remove TCG_TARGET_HAS_deposit_{i32,i64}
tcg: Remove TCG_TARGET_HAS_{s}extract_{i32,i64}
tcg/tci: Remove assertions for deposit and extract
tcg/tci: Provide TCG_TARGET_{s}extract_valid
tcg/sparc64: Use SRA, SRL for {s}extract_i64
tcg/s390x: Fold the ext{8,16,32}[us] cases into {s}extract
tcg/riscv: Use SRAIW, SRLIW for {s}extract_i64
tcg/riscv64: Fold the ext{8,16,32}[us] cases into {s}extract
tcg/ppc: Fold the ext{8,16,32}[us] cases into {s}extract
tcg/mips: Fold the ext{8,16,32}[us] cases into {s}extract
tcg/loongarch64: Fold the ext{8,16,32}[us] cases into {s}extract
tcg/arm: Add full [US]XT[BH] into {s}extract
tcg/aarch64: Expand extract with offset 0 with andi
tcg/aarch64: Provide TCG_TARGET_{s}extract_valid
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Compare: https://github.com/qemu/qemu/compare/d6430c17d711...32a97c5d05c5
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