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[Qemu-commits] [qemu/qemu] dd2911: target/loongarch: Add page table walk
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From: |
stefanhaRH |
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Subject: |
[Qemu-commits] [qemu/qemu] dd2911: target/loongarch: Add page table walker support fo... |
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Date: |
Thu, 16 Jan 2025 06:04:44 -0800 |
Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: dd291171740871a84c183d886f70b8d2e6a68d09
https://github.com/qemu/qemu/commit/dd291171740871a84c183d886f70b8d2e6a68d09
Author: Miao Hao <haomiao23s@ict.ac.cn>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M target/loongarch/cpu_helper.c
M target/loongarch/internals.h
M target/loongarch/tcg/tlb_helper.c
Log Message:
-----------
target/loongarch: Add page table walker support for debugger usage
When dump memory content with gva address, software page table walker is
necessary to get responding gpa address.
Here page table walker is added for debugger usage.
Signed-off-by: Miao Hao <haomiao23s@ict.ac.cn>
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
Commit: 59c54c1ceb1d84cb48d27a5b26d6f21cb76ee9e1
https://github.com/qemu/qemu/commit/59c54c1ceb1d84cb48d27a5b26d6f21cb76ee9e1
Author: Bibo Mao <maobibo@loongson.cn>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M hw/intc/loongarch_ipi.c
M include/hw/intc/loongarch_ipi.h
Log Message:
-----------
hw/intc/loongarch_ipi: Implement realize interface
Add realize interface for loongarch ipi device.
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
Commit: 5b82177addba2487c3c0e1b1974c0076a5a36342
https://github.com/qemu/qemu/commit/5b82177addba2487c3c0e1b1974c0076a5a36342
Author: Bibo Mao <maobibo@loongson.cn>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M hw/intc/loongarch_ipi.c
M hw/intc/loongson_ipi.c
M hw/intc/loongson_ipi_common.c
Log Message:
-----------
hw/intc/loongson_ipi: Remove num_cpu from loongson_ipi_common
With mips64 loongson ipi, num_cpu property is used. With loongarch
ipi, num_cpu can be acquired from possible_cpu_arch_ids.
Here remove num_cpu setting from loongson_ipi_common, and this piece
of code is put into loongson and loongarch ipi separately.
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
Commit: ce78dacf7e9b22dcc121dca17b1a3bcd93751680
https://github.com/qemu/qemu/commit/ce78dacf7e9b22dcc121dca17b1a3bcd93751680
Author: Bibo Mao <maobibo@loongson.cn>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M hw/intc/loongarch_ipi.c
M hw/intc/loongson_ipi.c
M hw/intc/loongson_ipi_common.c
Log Message:
-----------
hw/intc/loongson_ipi: Remove property num_cpu from loongson_ipi_common
With mips64 loongson ipi, num_cpu property is used. With loongarch
ipi, num_cpu can be acquired from possible_cpu_arch_ids.
Here remove property num_cpu from loongson_ipi_common, and put it into
loongson and loongarch ipi separately.
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
Commit: 14dc02b56a3d4434401ad92415cbec3e30ff3fa5
https://github.com/qemu/qemu/commit/14dc02b56a3d4434401ad92415cbec3e30ff3fa5
Author: Bibo Mao <maobibo@loongson.cn>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M hw/intc/loongarch_ipi.c
M include/hw/intc/loongson_ipi_common.h
Log Message:
-----------
hw/intc/loongarch_ipi: Get cpu number from possible_cpu_arch_ids
Supported CPU number can be acquired from function
possible_cpu_arch_ids(), cpu-num property is not necessary and can
be removed.
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
Commit: 1b3aa347044966a69e16a821eb44fbc16d0d58c9
https://github.com/qemu/qemu/commit/1b3aa347044966a69e16a821eb44fbc16d0d58c9
Author: Bibo Mao <maobibo@loongson.cn>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M hw/intc/loongarch_ipi.c
M hw/loongarch/virt.c
Log Message:
-----------
hw/intc/loongarch_ipi: Remove property num-cpu
Since cpu number can be acquired from possible_cpu_arch_ids(),
num-cpu property is not necessary. Here remove num-cpu property
for object TYPE_LOONGARCH_IPI object.
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
Commit: 999b112d90be8404547eec0793f8d7c0b5d2a547
https://github.com/qemu/qemu/commit/999b112d90be8404547eec0793f8d7c0b5d2a547
Author: Bibo Mao <maobibo@loongson.cn>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M hw/intc/loongarch_ipi.c
M hw/intc/loongson_ipi.c
M hw/intc/loongson_ipi_common.c
M include/hw/intc/loongson_ipi_common.h
Log Message:
-----------
hw/intc/loongson_ipi: Add more input parameter for cpu_by_arch_id
Add logic cpu index input parameter for function cpu_by_arch_id,
CPUState::cpu_index is logic cpu slot index for possible_cpus.
At the same time it is logic index with LoongsonIPICommonState::IPICore,
here hide access for CPUState::cpu_index directly, it comes from
function cpu_by_arch_id().
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
Commit: bb81f237401b5f89f6bba21d9d4f50e0073372a6
https://github.com/qemu/qemu/commit/bb81f237401b5f89f6bba21d9d4f50e0073372a6
Author: Bibo Mao <maobibo@loongson.cn>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M hw/intc/loongarch_ipi.c
Log Message:
-----------
hw/intc/loongarch_ipi: Use alternative implemation for cpu_by_arch_id
There is arch_id and CPUState pointer in IPICore object. With function
cpu_by_arch_id() it can be implemented by parsing IPICore array inside,
rather than possible_cpus array.
Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
Commit: e6cdeee95990a2c6f5d6873d3afb3c90518aed5c
https://github.com/qemu/qemu/commit/e6cdeee95990a2c6f5d6873d3afb3c90518aed5c
Author: David Woodhouse <dwmw@amazon.co.uk>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M hw/xen/trace-events
M hw/xen/xen-bus-helper.c
M include/hw/xen/xen-bus-helper.h
Log Message:
-----------
hw/xen: Add xs_node_read() helper function
This returns the full contents of the node, having created the node path
from the printf-style format string provided in its arguments.
This will save various callers from having to do so for themselves (and
from using xs_node_scanf() with the non-portable %ms format string.
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
[remove double newline and constify trace parameters]
Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
Reviewed-by: Anthony PERARD <anthony.perard@vates.tech>
Commit: 7a0b74d8716836f1206c5dfd778984c5d6eee46b
https://github.com/qemu/qemu/commit/7a0b74d8716836f1206c5dfd778984c5d6eee46b
Author: Roger Pau Monne <roger.pau@citrix.com>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M hw/block/xen-block.c
M hw/char/xen_console.c
M hw/xen/xen-bus.c
M include/hw/xen/xen-bus.h
Log Message:
-----------
xen: do not use '%ms' scanf specifier
The 'm' parameter used to request auto-allocation of the destination variable
is not supported on FreeBSD, and as such leads to failures to parse.
What's more, the current usage of '%ms' with xs_node_scanf() is pointless, as
it just leads to a double allocation of the same string. Instead use
xs_node_read() to read the whole xenstore node.
Fixes: a783f8ad4ec9 ('xen: add a mechanism to automatically create
XenDevice-s...')
Fixes: 9b7737469080 ('hw/xen: update Xen console to XenDevice model')
Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Anthony PERARD <anthony.perard@vates.tech>
Commit: 76f26e46ac577421e148adcedabfa12d4200ff3e
https://github.com/qemu/qemu/commit/76f26e46ac577421e148adcedabfa12d4200ff3e
Author: David Woodhouse <dwmw@amazon.co.uk>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M hw/xen/trace-events
M hw/xen/xen-bus-helper.c
Log Message:
-----------
hw/xen: Use xs_node_read() from xs_node_vscanf()
Reduce some duplication.
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Anthony PERARD <anthony.perard@vates.tech>
Acked-by: Roger Pau Monné <roger.pau@citrix.com>
Commit: b34729aca2f18a7c277bd2903b932add21cf7796
https://github.com/qemu/qemu/commit/b34729aca2f18a7c277bd2903b932add21cf7796
Author: David Woodhouse <dwmw@amazon.co.uk>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M hw/char/xen_console.c
Log Message:
-----------
hw/xen: Use xs_node_read() from xen_console_get_name()
Now that xs_node_read() can construct a node path, no need to open-code it.
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Anthony PERARD <anthony.perard@vates.tech>
Acked-by: Roger Pau Monné <roger.pau@citrix.com>
Commit: e4e113ecc2d2e4d1bc9d3a70bf01bba4b86f845c
https://github.com/qemu/qemu/commit/e4e113ecc2d2e4d1bc9d3a70bf01bba4b86f845c
Author: David Woodhouse <dwmw@amazon.co.uk>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M hw/net/xen_nic.c
Log Message:
-----------
hw/xen: Use xs_node_read() from xen_netdev_get_name()
Now that xs_node_read() can construct a node path, no need to open-code it.
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Anthony PERARD <anthony.perard@vates.tech>
Acked-by: Roger Pau Monné <roger.pau@citrix.com>
Commit: cd414c3f566fdbd98778c1c9a497428a80cd7fdd
https://github.com/qemu/qemu/commit/cd414c3f566fdbd98778c1c9a497428a80cd7fdd
Author: David Woodhouse <dwmw@amazon.co.uk>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M hw/xen/xen_pvdev.c
Log Message:
-----------
hw/xen: Use xs_node_read() from xenstore_read_str() instead of open-coding it
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Anthony PERARD <anthony.perard@vates.tech>
Acked-by: Roger Pau Monné <roger.pau@citrix.com>
Commit: 8b44a3e39f36540818d99ef8cf79e64bba1ed9c3
https://github.com/qemu/qemu/commit/8b44a3e39f36540818d99ef8cf79e64bba1ed9c3
Author: David Woodhouse <dwmw@amazon.co.uk>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M hw/char/xen_console.c
Log Message:
-----------
hw/xen: Fix errp handling in xen_console
When attempting to read the 'output' node, interpret any error *other*
than ENOENT as a fatal error. For ENOENT, fall back to serial_hd() to
find a character device, or create a null device.
Do not attempt to prepend to errp when serial_hd() fails; the error
isn't relevant (and prior to this change, wasn't set anyway).
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Anthony PERARD <anthony.perard@vates.tech>
Commit: e7bc0204e57836b3df611b73d2decc56ed698c4a
https://github.com/qemu/qemu/commit/e7bc0204e57836b3df611b73d2decc56ed698c4a
Author: Phil Dennis-Jordan <phil@philjordan.eu>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M include/system/system.h
M system/runstate.c
Log Message:
-----------
system/runstate: Fix regression, clarify BQL status of exit notifiers
By changing the way the main QEMU event loop is invoked, I inadvertently
changed the BQL status of exit notifiers: some of them implicitly
assumed they would be called with the BQL held; the BQL is however
not held during the exit(status) call in qemu_default_main().
Instead of attempting to ensuring we always call exit() from the BQL -
including any transitive calls - this change adds a BQL lock guard to
qemu_run_exit_notifiers, ensuring the BQL will always be held in the
exit notifiers.
Additionally, the BQL promise is now documented at the
qemu_{add,remove}_exit_notifier() declarations.
Fixes: f5ab12caba4f ("ui & main loop: Redesign of system-specific main
thread event handling")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2771
Reported-by: David Woodhouse <dwmw@amazon.co.uk>
Signed-off-by: Phil Dennis-Jordan <phil@philjordan.eu>
Tested-by: David Woodhouse <dwmw@amazon.co.uk>
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Commit: 1e77a4a32f8b7b6699a2f8b1f98e8fada902ba1f
https://github.com/qemu/qemu/commit/1e77a4a32f8b7b6699a2f8b1f98e8fada902ba1f
Author: Dorinda Bassey <dbassey@redhat.com>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M hw/display/vhost-user-gpu.c
M hw/display/virtio-gpu-base.c
M include/hw/virtio/virtio-gpu.h
Log Message:
-----------
virtio-gpu: Add definition for resource_uuid feature
Add the VIRTIO_GPU_F_RESOURCE_UUID feature to enable the assignment
of resources UUIDs for export to other virtio devices.
Signed-off-by: Dorinda Bassey <dbassey@redhat.com>
Message-Id: <20241007070013.3350752-1-dbassey@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 694632fd44987cc4618612a38ad151047524a590
https://github.com/qemu/qemu/commit/694632fd44987cc4618612a38ad151047524a590
Author: Sebastian Ott <sebott@redhat.com>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M hw/pci/pcie.c
Log Message:
-----------
pci: ensure valid link status bits for downstream ports
PCI hotplug for downstream endpoints on arm fails because Linux'
PCIe hotplug driver doesn't like the QEMU provided LNKSTA:
pcieport 0000:08:01.0: pciehp: Slot(2): Card present
pcieport 0000:08:01.0: pciehp: Slot(2): Link Up
pcieport 0000:08:01.0: pciehp: Slot(2): Cannot train link: status 0x2000
There's 2 cases where LNKSTA isn't setup properly:
* the downstream device has no express capability
* max link width of the bridge is 0
Move the sanity checks added via 88c869198aa63
("pci: Sanity test minimum downstream LNKSTA") outside of the
branch to make sure downstream ports always have a valid LNKSTA.
Signed-off-by: Sebastian Ott <sebott@redhat.com>
Tested-by: Zhenyu Zhang <zhenyzha@redhat.com>
Message-Id: <20241203121928.14861-1-sebott@redhat.com>
Reviewed-by: Alex Williamson <alex.williamson@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: e043be2290ffdd666ad2ab35d2341c137b21a3b4
https://github.com/qemu/qemu/commit/e043be2290ffdd666ad2ab35d2341c137b21a3b4
Author: Igor Mammedov <imammedo@redhat.com>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests: acpi: whitelist expected blobs
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20241210163945.3422623-2-imammedo@redhat.com>
Tested-by: Eric Mackay <eric.mackay@oracle.com>
Acked-by: Ani Sinha <anisinha@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 8aa35bebeeaed19ae57afbc3e110b8e7fe8587d0
https://github.com/qemu/qemu/commit/8aa35bebeeaed19ae57afbc3e110b8e7fe8587d0
Author: Igor Mammedov <imammedo@redhat.com>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M hw/acpi/cpu.c
Log Message:
-----------
cpuhp: make sure that remove events are handled within the same SCI
CPU_SCAN_METHOD was processing insert events first and only if insert event was
not present then it would check remove event.
Normally it's not an issue as it doesn't make much sense tho hotplug and
immediately unplug it. In this corner case, which can be reproduced with:
qemu -smp 1,maxcpus=2 -cpu host -monitor stdio \
-drive if=pflash,format=raw,readonly,file=edk2-x86_64-code.fd
* boot till GRUB prompt and pause guest (either via monitor or stop GRUB
from automatic boot)
* at monitor prompt add CPU:
device_add host-x86_64-cpu,socket-id=0,core-id=1,thread-id=0,id=foo
* let guest OS boot completely, and unplug CPU from monitor prompt:
device_del foo
which triggers GPE event that leads to CPU_SCAN_METHOD on guest side
as result of above cpu 'foo' will not be hotunplugged, since QEMU sees
insert event and ignores remove event (leaving it in pending state) for
the GPE event.
Any follow up CPU hotplug/unplug action from QEMU side will handle
previously ignored event, so as workaround user can repeat device_del.
Fix this corner-case by queuing remove events independently from insert
events, aka the same way as we do with insert events. And then go over remove
queue to send eject notify events to OSPM within the same GPE event.
PS:
Process remove queue after the cpu add queue has been processed 1st
to ensure that OSPM gets hotadd evets after hotremove ones.
PS2:
Case where it's still borken happens when guest OS is Linux and
device_del happens before guest OS initializes ACPI subsystem.
Culprit in this case though is the guest kernel, which mangles GPE.sts
(by clearing them up) and thus pending SCI turns to NOP leaving
insert/remove events in pending state.
That is the guest bug and should be fixed there.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reported-by: Eric Mackay <eric.mackay@oracle.com>
Message-Id: <20241210163945.3422623-3-imammedo@redhat.com>
Tested-by: Eric Mackay <eric.mackay@oracle.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 9ccb69df554a5204077cda101b7bcf0f19544553
https://github.com/qemu/qemu/commit/9ccb69df554a5204077cda101b7bcf0f19544553
Author: Igor Mammedov <imammedo@redhat.com>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M tests/data/acpi/x86/pc/DSDT
M tests/data/acpi/x86/pc/DSDT.acpierst
M tests/data/acpi/x86/pc/DSDT.acpihmat
M tests/data/acpi/x86/pc/DSDT.bridge
M tests/data/acpi/x86/pc/DSDT.cphp
M tests/data/acpi/x86/pc/DSDT.dimmpxm
M tests/data/acpi/x86/pc/DSDT.hpbridge
M tests/data/acpi/x86/pc/DSDT.hpbrroot
M tests/data/acpi/x86/pc/DSDT.ipmikcs
M tests/data/acpi/x86/pc/DSDT.memhp
M tests/data/acpi/x86/pc/DSDT.nohpet
M tests/data/acpi/x86/pc/DSDT.numamem
M tests/data/acpi/x86/pc/DSDT.roothp
M tests/data/acpi/x86/q35/DSDT
M tests/data/acpi/x86/q35/DSDT.acpierst
M tests/data/acpi/x86/q35/DSDT.acpihmat
M tests/data/acpi/x86/q35/DSDT.acpihmat-generic-x
M tests/data/acpi/x86/q35/DSDT.acpihmat-noinitiator
M tests/data/acpi/x86/q35/DSDT.applesmc
M tests/data/acpi/x86/q35/DSDT.bridge
M tests/data/acpi/x86/q35/DSDT.core-count
M tests/data/acpi/x86/q35/DSDT.core-count2
M tests/data/acpi/x86/q35/DSDT.cphp
M tests/data/acpi/x86/q35/DSDT.cxl
M tests/data/acpi/x86/q35/DSDT.dimmpxm
M tests/data/acpi/x86/q35/DSDT.ipmibt
M tests/data/acpi/x86/q35/DSDT.ipmismbus
M tests/data/acpi/x86/q35/DSDT.ivrs
M tests/data/acpi/x86/q35/DSDT.memhp
M tests/data/acpi/x86/q35/DSDT.mmio64
M tests/data/acpi/x86/q35/DSDT.multi-bridge
M tests/data/acpi/x86/q35/DSDT.noacpihp
M tests/data/acpi/x86/q35/DSDT.nohpet
M tests/data/acpi/x86/q35/DSDT.numamem
M tests/data/acpi/x86/q35/DSDT.pvpanic-isa
M tests/data/acpi/x86/q35/DSDT.thread-count
M tests/data/acpi/x86/q35/DSDT.thread-count2
M tests/data/acpi/x86/q35/DSDT.tis.tpm12
M tests/data/acpi/x86/q35/DSDT.tis.tpm2
M tests/data/acpi/x86/q35/DSDT.type4-count
M tests/data/acpi/x86/q35/DSDT.viot
M tests/data/acpi/x86/q35/DSDT.xapic
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests: acpi: update expected blobs
previous patch has changed cpu hotplug AML, expected diff:
@@ -2942,6 +2942,7 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ",
0x00000001)
{
Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF)
Name (CNEW, Package (0xFF) {})
+ Name (CEJL, Package (0xFF) {})
Local3 = Zero
Local4 = One
While ((Local4 == One))
@@ -2949,6 +2950,7 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ",
0x00000001)
Local4 = Zero
Local0 = One
Local1 = Zero
+ Local5 = Zero
While (((Local0 == One) && (Local3 < One)))
{
Local0 = Zero
@@ -2959,7 +2961,7 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ",
0x00000001)
Break
}
- If ((Local1 == 0xFF))
+ If (((Local1 == 0xFF) || (Local5 == 0xFF)))
{
Local4 = One
Break
@@ -2972,10 +2974,11 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ",
0x00000001)
Local1++
Local0 = One
}
- ElseIf ((\_SB.PCI0.PRES.CRMV == One))
+
+ If ((\_SB.PCI0.PRES.CRMV == One))
{
- CTFY (Local3, 0x03)
- \_SB.PCI0.PRES.CRMV = One
+ CEJL [Local5] = Local3
+ Local5++
Local0 = One
}
@@ -2992,6 +2995,16 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ",
0x00000001)
\_SB.PCI0.PRES.CINS = One
Local2++
}
+
+ Local2 = Zero
+ While ((Local2 < Local5))
+ {
+ Local3 = DerefOf (CEJL [Local2])
+ CTFY (Local3, 0x03)
+ \_SB.PCI0.PRES.CSEL = Local3
+ \_SB.PCI0.PRES.CRMV = One
+ Local2++
+ }
}
Release (\_SB.PCI0.PRES.CPLK)
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20241210163945.3422623-4-imammedo@redhat.com>
Tested-by: Eric Mackay <eric.mackay@oracle.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: a84e37af36ca89880395bf999873f1a477bf6fa7
https://github.com/qemu/qemu/commit/a84e37af36ca89880395bf999873f1a477bf6fa7
Author: Yu Zhang <yu.c.zhang@linux.intel.com>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M hw/i386/intel_iommu.c
M hw/i386/intel_iommu_internal.h
Log Message:
-----------
intel_iommu: Use the latest fault reasons defined by spec
Spec revision 3.0 or above defines more detailed fault reasons for
scalable mode. So introduce them into emulation code, see spec
section 7.1.2 for details.
Note spec revision has no relation with VERSION register, Guest
kernel should not use that register to judge what features are
supported. Instead cap/ecap bits should be checked.
Signed-off-by: Yu Zhang <yu.c.zhang@linux.intel.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com>
Reviewed-by: Yi Liu <yi.l.liu@intel.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20241212083757.605022-2-zhenzhong.duan@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: b291dae33d1dab48670b86807a71cb1cbadf39aa
https://github.com/qemu/qemu/commit/b291dae33d1dab48670b86807a71cb1cbadf39aa
Author: Zhenzhong Duan <zhenzhong.duan@intel.com>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M hw/i386/intel_iommu.c
Log Message:
-----------
intel_iommu: Make pasid entry type check accurate
When guest configures Nested Translation(011b) or First-stage Translation only
(001b), type check passed unaccurately.
Fails the type check in those cases as their simulation isn't supported yet.
Fixes: fb43cf739e1 ("intel_iommu: scalable mode emulation")
Suggested-by: Yi Liu <yi.l.liu@intel.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com>
Reviewed-by: Yi Liu <yi.l.liu@intel.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20241212083757.605022-3-zhenzhong.duan@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 791346f93d2aa3b7eaebf4a12f4b7c558e94ff6b
https://github.com/qemu/qemu/commit/791346f93d2aa3b7eaebf4a12f4b7c558e94ff6b
Author: Zhenzhong Duan <zhenzhong.duan@intel.com>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M hw/i386/intel_iommu.c
M include/hw/i386/intel_iommu.h
Log Message:
-----------
intel_iommu: Add a placeholder variable for scalable mode stage-1 translation
Add an new element flts in IntelIOMMUState to mark stage-1 translation support
in scalable mode, this element will be exposed as an intel_iommu property
x-flts finally.
For now, it's only a placehholder and used for address width compatibility
check and block host device passthrough until nesting is supported.
Signed-off-by: Yi Liu <yi.l.liu@intel.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com>
Reviewed-by: Yi Liu <yi.l.liu@intel.com>
Message-Id: <20241212083757.605022-4-zhenzhong.duan@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: ad0a7f1e1edbe841d4285a6b56f071eb3de9c86c
https://github.com/qemu/qemu/commit/ad0a7f1e1edbe841d4285a6b56f071eb3de9c86c
Author: Zhenzhong Duan <zhenzhong.duan@intel.com>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M hw/i386/intel_iommu.c
M hw/i386/intel_iommu_internal.h
Log Message:
-----------
intel_iommu: Flush stage-2 cache in PASID-selective PASID-based iotlb
invalidation
Per VT-d spec 4.1, 6.5.2.4, "Table 21. PASID-based-IOTLB Invalidation",
PADID-selective PASID-based iotlb invalidation will flush stage-2 iotlb
entries with matching domain id and pasid.
With stage-1 translation introduced, guest could send PASID-selective
PASID-based iotlb invalidation to flush either stage-1 or stage-2 entries.
By this chance, remove old IOTLB related definitions which were unused.
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20241212083757.605022-5-zhenzhong.duan@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: eda4c9b5b3c46f8d4d6a628cc7a588f187f30050
https://github.com/qemu/qemu/commit/eda4c9b5b3c46f8d4d6a628cc7a588f187f30050
Author: Yi Liu <yi.l.liu@intel.com>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M hw/i386/intel_iommu.c
M hw/i386/intel_iommu_internal.h
M include/hw/i386/intel_iommu.h
Log Message:
-----------
intel_iommu: Rename slpte to pte
Because we will support both FST(a.k.a, FLT) and SST(a.k.a, SLT) translation,
rename variable and functions from slpte to pte whenever possible.
But some are SST only, they are renamed with sl_ prefix.
Signed-off-by: Yi Liu <yi.l.liu@intel.com>
Co-developed-by: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com>
Signed-off-by: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com>
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Reviewed-by: Yi Liu <yi.l.liu@intel.com>
Message-Id: <20241212083757.605022-6-zhenzhong.duan@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: eb9da9d2632839c386ecbfc50f78032c9f3a75a4
https://github.com/qemu/qemu/commit/eb9da9d2632839c386ecbfc50f78032c9f3a75a4
Author: Yi Liu <yi.l.liu@intel.com>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M hw/i386/intel_iommu.c
M hw/i386/intel_iommu_internal.h
Log Message:
-----------
intel_iommu: Implement stage-1 translation
This adds stage-1 page table walking to support stage-1 only
translation in scalable mode.
Signed-off-by: Yi Liu <yi.l.liu@intel.com>
Co-developed-by: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com>
Signed-off-by: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com>
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20241212083757.605022-7-zhenzhong.duan@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 305e469b7188e5f1a896c40853d84fa158ee6ba4
https://github.com/qemu/qemu/commit/305e469b7188e5f1a896c40853d84fa158ee6ba4
Author: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M hw/i386/intel_iommu.c
M hw/i386/intel_iommu_internal.h
Log Message:
-----------
intel_iommu: Check if the input address is canonical
Stage-1 translation must fail if the address to translate is
not canonical.
Signed-off-by: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Reviewed-by: Yi Liu <yi.l.liu@intel.com>
Message-Id: <20241212083757.605022-8-zhenzhong.duan@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: fed51ee5e02d8779ccbdce555e556c4ada321281
https://github.com/qemu/qemu/commit/fed51ee5e02d8779ccbdce555e556c4ada321281
Author: Zhenzhong Duan <zhenzhong.duan@intel.com>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M hw/i386/intel_iommu.c
Log Message:
-----------
intel_iommu: Check stage-1 translation result with interrupt range
Per VT-d spec 4.1 section 3.15, "Untranslated requests and translation
requests that result in an address in the interrupt range will be
blocked with condition code LGN.4 or SGN.8."
This applies to both stage-1 and stage-2 IOMMU page table, move the
check from vtd_iova_to_slpte() to vtd_do_iommu_translate() so stage-1
page table could also be checked.
By this chance, update the comment with correct section number.
Suggested-by: Yi Liu <yi.l.liu@intel.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20241212083757.605022-9-zhenzhong.duan@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 65c4f0999991f6321d6a369fa56c81c57c5b87ad
https://github.com/qemu/qemu/commit/65c4f0999991f6321d6a369fa56c81c57c5b87ad
Author: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M hw/i386/intel_iommu.c
M hw/i386/intel_iommu_internal.h
Log Message:
-----------
intel_iommu: Set accessed and dirty bits during stage-1 translation
Signed-off-by: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Reviewed-by: Yi Liu <yi.l.liu@intel.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20241212083757.605022-10-zhenzhong.duan@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 16d4e418e98feeb53f28d17eeffb198fe0fd6f22
https://github.com/qemu/qemu/commit/16d4e418e98feeb53f28d17eeffb198fe0fd6f22
Author: Zhenzhong Duan <zhenzhong.duan@intel.com>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M hw/i386/intel_iommu.c
M include/hw/i386/intel_iommu.h
Log Message:
-----------
intel_iommu: Flush stage-1 cache in iotlb invalidation
According to spec, Page-Selective-within-Domain Invalidation (11b):
1. IOTLB entries caching second-stage mappings (PGTT=010b) or pass-through
(PGTT=100b) mappings associated with the specified domain-id and the
input-address range are invalidated.
2. IOTLB entries caching first-stage (PGTT=001b) or nested (PGTT=011b)
mapping associated with specified domain-id are invalidated.
So per spec definition the Page-Selective-within-Domain Invalidation
needs to flush first stage and nested cached IOTLB entries as well.
We don't support nested yet and pass-through mapping is never cached,
so what in iotlb cache are only first-stage and second-stage mappings.
Add a tag pgtt in VTDIOTLBEntry to mark PGTT type of the mapping and
invalidate entries based on PGTT type.
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Reviewed-by: Yi Liu <yi.l.liu@intel.com>
Message-Id: <20241212083757.605022-11-zhenzhong.duan@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 6ebe6cf2a0663f46f94a69eca5296f608da12f2e
https://github.com/qemu/qemu/commit/6ebe6cf2a0663f46f94a69eca5296f608da12f2e
Author: Zhenzhong Duan <zhenzhong.duan@intel.com>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M hw/i386/intel_iommu.c
M hw/i386/intel_iommu_internal.h
Log Message:
-----------
intel_iommu: Process PASID-based iotlb invalidation
PASID-based iotlb (piotlb) is used during walking Intel
VT-d stage-1 page table.
This emulates the stage-1 page table iotlb invalidation requested
by a PASID-based IOTLB Invalidate Descriptor (P_IOTLB).
Signed-off-by: Yi Liu <yi.l.liu@intel.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Reviewed-by: Yi Liu <yi.l.liu@intel.com>
Message-Id: <20241212083757.605022-12-zhenzhong.duan@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 1075645d430e291404d19c88fc80d989669fa4c8
https://github.com/qemu/qemu/commit/1075645d430e291404d19c88fc80d989669fa4c8
Author: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M hw/i386/intel_iommu.c
Log Message:
-----------
intel_iommu: Add an internal API to find an address space with PASID
This will be used to implement the device IOTLB invalidation
Signed-off-by: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Reviewed-by: Yi Liu <yi.l.liu@intel.com>
Message-Id: <20241212083757.605022-13-zhenzhong.duan@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: dd8200503e230a4e32f930f5a57556b04651c16f
https://github.com/qemu/qemu/commit/dd8200503e230a4e32f930f5a57556b04651c16f
Author: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M hw/i386/intel_iommu.c
M hw/i386/intel_iommu_internal.h
Log Message:
-----------
intel_iommu: Add support for PASID-based device IOTLB invalidation
Signed-off-by: Clément Mathieu--Drif <clement.mathieu--drif@eviden.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20241212083757.605022-14-zhenzhong.duan@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 1ab93575bdcb2972c99a174a957b598f7457a899
https://github.com/qemu/qemu/commit/1ab93575bdcb2972c99a174a957b598f7457a899
Author: Zhenzhong Duan <zhenzhong.duan@intel.com>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M hw/i386/intel_iommu.c
Log Message:
-----------
intel_iommu: piotlb invalidation should notify unmap
This is used by some emulated devices which caches address
translation result. When piotlb invalidation issued in guest,
those caches should be refreshed.
There is already a similar implementation in iotlb invalidation.
So update vtd_iotlb_page_invalidate_notify() to make it work
also for piotlb invalidation.
For device that does not implement ATS capability or disable
it but still caches the translation result, it is better to
implement ATS cap or enable it if there is need to cache the
translation result.
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com>
Message-Id: <20241212083757.605022-15-zhenzhong.duan@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 9609d7101867819086516c7df845337dcee1cf08
https://github.com/qemu/qemu/commit/9609d7101867819086516c7df845337dcee1cf08
Author: Zhenzhong Duan <zhenzhong.duan@intel.com>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests/acpi: q35: allow DMAR acpi table changes
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20241212083757.605022-16-zhenzhong.duan@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: ddd84fd0c1f8f62e8384591f7203aaabb935199a
https://github.com/qemu/qemu/commit/ddd84fd0c1f8f62e8384591f7203aaabb935199a
Author: Zhenzhong Duan <zhenzhong.duan@intel.com>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M hw/i386/pc.c
M include/hw/i386/intel_iommu.h
Log Message:
-----------
intel_iommu: Set default aw_bits to 48 starting from QEMU 9.2
According to VTD spec, stage-1 page table could support 4-level and
5-level paging.
However, 5-level paging translation emulation is unsupported yet.
That means the only supported value for aw_bits is 48. So default
aw_bits to 48 when stage-1 translation is turned on.
For legacy and scalable modes, 48 is the default choice for modern
OS when both 48 and 39 are supported. So it makes sense to set
default to 48 for these two modes too starting from QEMU 9.2.
Use pc_compat_9_1 to handle the compatibility for machines before
9.2.
Suggested-by: Jason Wang <jasowang@redhat.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com>
Reviewed-by: Yi Liu <yi.l.liu@intel.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20241212083757.605022-17-zhenzhong.duan@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 81ab964f21620db32558277f220eb0d803c14109
https://github.com/qemu/qemu/commit/81ab964f21620db32558277f220eb0d803c14109
Author: Zhenzhong Duan <zhenzhong.duan@intel.com>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M tests/data/acpi/x86/q35/DMAR.dmar
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests/acpi: q35: Update host address width in DMAR
Differences:
@@ -1,39 +1,39 @@
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20200925 (64-bit version)
* Copyright (c) 2000 - 2020 Intel Corporation
*
- * Disassembly of tests/data/acpi/x86/q35/DMAR.dmar, Mon Nov 11 15:31:18 2024
+ * Disassembly of /tmp/aml-SPJ4W2, Mon Nov 11 15:31:18 2024
*
* ACPI Data Table [DMAR]
*
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue
*/
[000h 0000 4] Signature : "DMAR" [DMA Remapping table]
[004h 0004 4] Table Length : 00000078
[008h 0008 1] Revision : 01
-[009h 0009 1] Checksum : 15
+[009h 0009 1] Checksum : 0C
[00Ah 0010 6] Oem ID : "BOCHS "
[010h 0016 8] Oem Table ID : "BXPC "
[018h 0024 4] Oem Revision : 00000001
[01Ch 0028 4] Asl Compiler ID : "BXPC"
[020h 0032 4] Asl Compiler Revision : 00000001
-[024h 0036 1] Host Address Width : 26
+[024h 0036 1] Host Address Width : 2F
[025h 0037 1] Flags : 01
[026h 0038 10] Reserved : 00 00 00 00 00 00 00 00 00 00
[030h 0048 2] Subtable Type : 0000 [Hardware Unit Definition]
[032h 0050 2] Length : 0040
[034h 0052 1] Flags : 00
[035h 0053 1] Reserved : 00
[036h 0054 2] PCI Segment Number : 0000
[038h 0056 8] Register Base Address : 00000000FED90000
[040h 0064 1] Device Scope Type : 03 [IOAPIC Device]
[041h 0065 1] Entry Length : 08
[042h 0066 2] Reserved : 0000
[044h 0068 1] Enumeration ID : 00
[045h 0069 1] PCI Bus Number : FF
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Acked-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com>
Message-Id: <20241212083757.605022-18-zhenzhong.duan@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: aa68a9fbdb81c47c2a48a3199559df470c3d9eba
https://github.com/qemu/qemu/commit/aa68a9fbdb81c47c2a48a3199559df470c3d9eba
Author: Zhenzhong Duan <zhenzhong.duan@intel.com>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M hw/i386/intel_iommu.c
M hw/i386/intel_iommu_internal.h
Log Message:
-----------
intel_iommu: Introduce a property x-flts for stage-1 translation
Intel VT-d 3.0 introduces scalable mode, and it has a bunch of capabilities
related to scalable mode translation, thus there are multiple combinations.
This vIOMMU implementation wants to simplify it with a new property "x-flts".
When turned on in scalable mode, stage-1 translation is supported. When turned
on in legacy mode, throw out error.
With stage-1 translation support exposed to user, also accurate the pasid entry
check in vtd_pe_type_check().
Suggested-by: Jason Wang <jasowang@redhat.com>
Signed-off-by: Yi Liu <yi.l.liu@intel.com>
Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com>
Message-Id: <20241212083757.605022-19-zhenzhong.duan@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: d9d32478ed4543539322761c19a73edf5d0be059
https://github.com/qemu/qemu/commit/d9d32478ed4543539322761c19a73edf5d0be059
Author: Zhenzhong Duan <zhenzhong.duan@intel.com>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M hw/i386/intel_iommu.c
M include/hw/i386/intel_iommu.h
Log Message:
-----------
intel_iommu: Introduce a property to control FS1GP cap bit setting
This gives user flexibility to turn off FS1GP for debug purpose.
It is also useful for future nesting feature. When host IOMMU doesn't
support FS1GP but vIOMMU does, nested page table on host side works
after turning FS1GP off in vIOMMU.
This property has no effect when vIOMMU is in legacy mode or x-flts=off
in scalable modme.
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com>
Reviewed-by: Yi Liu <yi.l.liu@intel.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20241212083757.605022-20-zhenzhong.duan@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 2c746dfe1c69896b0e434d37efe014654f0a3a65
https://github.com/qemu/qemu/commit/2c746dfe1c69896b0e434d37efe014654f0a3a65
Author: Zhenzhong Duan <zhenzhong.duan@intel.com>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M MAINTAINERS
M include/hw/i386/intel_iommu.h
A tests/qtest/intel-iommu-test.c
M tests/qtest/meson.build
Log Message:
-----------
tests/qtest: Add intel-iommu test
Add the framework to test the intel-iommu device.
Currently only tested cap/ecap bits correctness when x-flts=on in scalable
mode. Also tested cap/ecap bits consistency before and after system reset.
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
Acked-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Clément Mathieu--Drif<clement.mathieu--drif@eviden.com>
Acked-by: Jason Wang <jasowang@redhat.com>
Message-Id: <20241212083757.605022-21-zhenzhong.duan@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 42e2a7a0ab23784e44fcb18369e06067abc89305
https://github.com/qemu/qemu/commit/42e2a7a0ab23784e44fcb18369e06067abc89305
Author: Nicholas Piggin <npiggin@gmail.com>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M hw/pci/msix.c
Log Message:
-----------
pci/msix: Fix msix pba read vector poll end calculation
The end vector calculation has a bug that results in polling fewer
than required vectors when reading at a non-zero offset in PBA memory.
Fixes: bbef882cc193 ("msi: add API to get notified about pending bit poll")
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-Id: <20241212120402.1475053-1-npiggin@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 239c3f7ed44d8b82a682a1c2e9e8c3355c10d321
https://github.com/qemu/qemu/commit/239c3f7ed44d8b82a682a1c2e9e8c3355c10d321
Author: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M hw/acpi/ghes.c
M include/hw/acpi/ghes.h
Log Message:
-----------
acpi/ghes: get rid of ACPI_HEST_SRC_ID_RESERVED
This is just duplicating ACPI_GHES_ERROR_SOURCE_COUNT, which
has a better name. So, drop the duplication.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id:
<9012bf4c9630adf15a22af3c88fda8270916887b.1736945236.git.mchehab+huawei@kernel.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 872b69f21fe34f133982e02d04e33425d761d33b
https://github.com/qemu/qemu/commit/872b69f21fe34f133982e02d04e33425d761d33b
Author: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M hw/acpi/ghes.c
Log Message:
-----------
acpi/ghes: simplify acpi_ghes_record_errors() code
Reduce the ident of the function and prepares it for
the next changes.
No functional changes.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id:
<19af4188535217213486d169e0501e592bc78a95.1736945236.git.mchehab+huawei@kernel.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 606a42c4c1d46b31a95cab09a7033e7f22f9ed3d
https://github.com/qemu/qemu/commit/606a42c4c1d46b31a95cab09a7033e7f22f9ed3d
Author: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M hw/acpi/ghes.c
M hw/arm/virt-acpi-build.c
M include/hw/acpi/ghes.h
Log Message:
-----------
acpi/ghes: simplify the per-arch caller to build HEST table
The GHES driver requires not only a HEST table, but also a
separate firmware file to store Error Structure records.
It can't do one without the other.
Simplify the caller logic for it to require one function.
No functional changes.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Message-Id:
<9584bb8953385e165681d5d185c503f8df8ef42f.1736945236.git.mchehab+huawei@kernel.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: a85a3b729b3c31d8cc878017308997a8112655b2
https://github.com/qemu/qemu/commit/a85a3b729b3c31d8cc878017308997a8112655b2
Author: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M hw/acpi/ghes.c
Log Message:
-----------
acpi/ghes: better handle source_id and notification
GHES has two fields that are stored on HEST error source
blocks associated with notifications:
- notification type, which is a number defined at the ACPI spec
containing several arch-specific synchronous and assynchronous
types;
- source id, which is a HW/FW defined number, used to distinguish
between different implemented sources.
There could be several sources with the same notification type,
which is dependent of the way each architecture maps notifications.
Right now, build_ghes_v2() hardcodes a 1:1 mapping between such
fields. Move it to two independent parameters, allowing the
caller function to fill both.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Message-Id:
<133ff72ea1041fed7dbcf97b7a2b0f4dfacde31a.1736945236.git.mchehab+huawei@kernel.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 5eb07a4ff067053b4d6bf55d2d614b65b00a476b
https://github.com/qemu/qemu/commit/5eb07a4ff067053b4d6bf55d2d614b65b00a476b
Author: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M include/hw/acpi/ghes.h
Log Message:
-----------
acpi/ghes: Fix acpi_ghes_record_errors() argument
Align the header file with the actual implementation of
this function, as the first argument is source ID and not
notification type.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Message-Id:
<d55f2a6ede5a168e42a20a228b2c066cb4c60939.1736945236.git.mchehab+huawei@kernel.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 4ffedca347c458db17c464f9329222403fe54f22
https://github.com/qemu/qemu/commit/4ffedca347c458db17c464f9329222403fe54f22
Author: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M hw/acpi/ghes.c
Log Message:
-----------
acpi/ghes: Remove a duplicated out of bounds check
acpi_ghes_record_errors() has an assert() at the beginning
to ensure that source_id will be lower than
ACPI_GHES_ERROR_SOURCE_COUNT. Remove a duplicated check.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id:
<df33b004d85b7b9aa388fb2ac530dcdea94b7edc.1736945236.git.mchehab+huawei@kernel.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 26e0893e420b34677e6e904a06edf55331bd937c
https://github.com/qemu/qemu/commit/26e0893e420b34677e6e904a06edf55331bd937c
Author: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M hw/acpi/ghes-stub.c
M hw/acpi/ghes.c
M include/hw/acpi/ghes.h
Log Message:
-----------
acpi/ghes: Change the type for source_id
As described at: ACPI 6.5 spec at:
18.3.2. ACPI Error Source
In particular at GHES/GHESv2 table:
Table 18.10 Generic Hardware Error Source Structure
HEST source ID is actually a 16-bit value.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Message-Id:
<0e83ba548c1aedd1299fe387b94db78986590a34.1736945236.git.mchehab+huawei@kernel.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 2e223c5ec1146b61163d3372ac629d9240d57cb1
https://github.com/qemu/qemu/commit/2e223c5ec1146b61163d3372ac629d9240d57cb1
Author: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M hw/acpi/ghes.c
Log Message:
-----------
acpi/ghes: don't check if physical_address is not zero
The 'physical_address' value is a faulty page. As such, 0 is
as valid as any other value.
Suggested-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id:
<da32536bf4962e5c03471e2a4e6e0ef92be4a1be.1736945236.git.mchehab+huawei@kernel.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 48b0dcdd67d3fafbd07f6298257259dec4f541ce
https://github.com/qemu/qemu/commit/48b0dcdd67d3fafbd07f6298257259dec4f541ce
Author: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M hw/acpi/ghes.c
M include/hw/acpi/ghes.h
Log Message:
-----------
acpi/ghes: make the GHES record generation more generic
Split the code into separate functions to allow using the
common CPER filling code by different error sources.
The generic code was moved to ghes_record_cper_errors(),
and ghes_gen_err_data_uncorrectable_recoverable() now contains
only a logic to fill the Generic Error Data part of the record,
as described at:
ACPI 6.2: 18.3.2.7.1 Generic Error Data
The remaining code to generate a memory error now belongs to
acpi_ghes_record_errors() function.
A further patch will give it a better name.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id:
<68d9f787d8c4fc8d1dbc227d6902fe801e42dea9.1736945236.git.mchehab+huawei@kernel.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: d32028a54000db671eb2d0b6b28bbf15acc2e5f9
https://github.com/qemu/qemu/commit/d32028a54000db671eb2d0b6b28bbf15acc2e5f9
Author: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M hw/acpi/ghes-stub.c
M hw/acpi/ghes.c
M include/hw/acpi/ghes.h
M target/arm/kvm.c
Log Message:
-----------
acpi/ghes: better name GHES memory error function
The current function used to generate GHES data is specific for
memory errors. Give a better name for it, as we now have a generic
function as well.
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Message-Id:
<35b59121129d5e99cb5062cc3d775594bbb0905b.1736945236.git.mchehab+huawei@kernel.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 1acc8d4e647e3d9fc45cc43c216e784e47a74809
https://github.com/qemu/qemu/commit/1acc8d4e647e3d9fc45cc43c216e784e47a74809
Author: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M hw/acpi/ghes.c
Log Message:
-----------
acpi/ghes: don't crash QEMU if ghes GED is not found
Make error handling within ghes_record_cper_errors() consistent,
i.e. instead abort just print a error in case ghes GED is not found.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Message-Id:
<c7e1665ba46df321f0ce161d60dfd681ab827535.1736945236.git.mchehab+huawei@kernel.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 4651745dfc8d384bd260969c23d8423741462eac
https://github.com/qemu/qemu/commit/4651745dfc8d384bd260969c23d8423741462eac
Author: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M hw/acpi/ghes.c
Log Message:
-----------
acpi/ghes: rename etc/hardware_error file macros
Now that we have also have a file to store HEST data location,
which is part of GHES, better name the file where CPER records
are stored.
No functional changes.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id:
<e79a013bcd9f634b46ff6b34756d1b1403713af3.1736945236.git.mchehab+huawei@kernel.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 652f6d86cbb60e193edc2510c365b75229734ccf
https://github.com/qemu/qemu/commit/652f6d86cbb60e193edc2510c365b75229734ccf
Author: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M hw/acpi/generic_event_device.c
M hw/acpi/ghes.c
M include/hw/acpi/ghes.h
Log Message:
-----------
acpi/ghes: better name the offset of the hardware error firmware
The hardware error firmware is where HEST error structures are
stored. Those can be GHESv2, but they can also be other types.
Better name the location of the hardware error.
No functional changes.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Message-Id:
<ddbb94294bafee998f12fede3ba0b05dae5ee45f.1736945236.git.mchehab+huawei@kernel.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 1cd59b8981ce234c1d790111afce4a32218a88dd
https://github.com/qemu/qemu/commit/1cd59b8981ce234c1d790111afce4a32218a88dd
Author: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M hw/acpi/ghes.c
Log Message:
-----------
acpi/ghes: move offset calculus to a separate function
Currently, CPER address location is calculated as an offset of
the hardware_errors table. It is also badly named, as the
offset actually used is the address where the CPER data starts,
and not the beginning of the error source.
Move the logic which calculates such offset to a separate
function, in preparation for a patch that will be changing the
logic to calculate it from the HEST table.
While here, properly name the variable which stores the cper
address.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id:
<60fdd1bf379ba1db3099710868802aa49a27febb.1736945236.git.mchehab+huawei@kernel.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 47935fc1e56f02c892d186ef89be7c923f73c89b
https://github.com/qemu/qemu/commit/47935fc1e56f02c892d186ef89be7c923f73c89b
Author: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M hw/acpi/ghes.c
Log Message:
-----------
acpi/ghes: Change ghes fill logic to work with only one source
Extending to multiple sources require a BIOS pointer to the
beginning of the HEST table, which in turn requires a backward-compatible
code.
So, the current code supports only one source. Ensure that and simplify
the code.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Message-Id:
<66bddd42a64c8515ad98b9975d953b4a70ffcc6d.1736945236.git.mchehab+huawei@kernel.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 84c146758d79b3689b6c9c7815b6bfbb70ba06b0
https://github.com/qemu/qemu/commit/84c146758d79b3689b6c9c7815b6bfbb70ba06b0
Author: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M docs/specs/acpi_hest_ghes.rst
Log Message:
-----------
docs: acpi_hest_ghes: fix documentation for CPER size
While the spec defines a CPER size of 4KiB for each record,
currently it is set to 1KiB. Fix the documentation and add
a pointer to the macro name there, as this may help to keep
it updated.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Message-Id:
<f7e94433bec19a9d6b23ecccc24b5fe3a6f7f52b.1736945236.git.mchehab+huawei@kernel.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 1ad32644fe4c9fb25086be15a66dde1d55d3410f
https://github.com/qemu/qemu/commit/1ad32644fe4c9fb25086be15a66dde1d55d3410f
Author: Igor Mammedov <imammedo@redhat.com>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests: acpi: whitelist expected blobs
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20250115125342.3883374-2-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 0b053391985abcc40b16ac8fc4a7f6588d1d95c1
https://github.com/qemu/qemu/commit/0b053391985abcc40b16ac8fc4a7f6588d1d95c1
Author: Igor Mammedov <imammedo@redhat.com>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M hw/i386/acpi-build.c
Log Message:
-----------
pci: acpi: Windows 'PCI Label Id' bug workaround
Current versions of Windows call _DSM(func=7) regardless
of whether it is supported or not. It leads to NICs having bogus
'PCI Label Id = 0', where none should be set at all.
Also presence of 'PCI Label Id' triggers another Windows bug
on localized versions that leads to hangs. The later bug is fixed
in latest updates for 'Windows Server' but not in consumer
versions of Windows (and there is no plans to fix it
as far as I'm aware).
Given it's easy, implement Microsoft suggested workaround
(return invalid Package) so that affected Windows versions
could boot on QEMU.
This would effectvely remove bogus 'PCI Label Id's on NICs,
but MS teem confirmed that flipping 'PCI Label Id' should not
change 'Network Connection' ennumeration, so it should be safe
for QEMU to change _DSM without any compat code.
Smoke tested with WinXP and WS2022
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/774
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20250115125342.3883374-3-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 9fb1c9a1bb26e111ee5fa5538070cd684de14c08
https://github.com/qemu/qemu/commit/9fb1c9a1bb26e111ee5fa5538070cd684de14c08
Author: Igor Mammedov <imammedo@redhat.com>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M tests/data/acpi/x86/pc/DSDT
M tests/data/acpi/x86/pc/DSDT.acpierst
M tests/data/acpi/x86/pc/DSDT.acpihmat
M tests/data/acpi/x86/pc/DSDT.bridge
M tests/data/acpi/x86/pc/DSDT.cphp
M tests/data/acpi/x86/pc/DSDT.dimmpxm
M tests/data/acpi/x86/pc/DSDT.hpbridge
M tests/data/acpi/x86/pc/DSDT.ipmikcs
M tests/data/acpi/x86/pc/DSDT.memhp
M tests/data/acpi/x86/pc/DSDT.nohpet
M tests/data/acpi/x86/pc/DSDT.numamem
M tests/data/acpi/x86/pc/DSDT.roothp
M tests/data/acpi/x86/q35/DSDT
M tests/data/acpi/x86/q35/DSDT.acpierst
M tests/data/acpi/x86/q35/DSDT.acpihmat
M tests/data/acpi/x86/q35/DSDT.acpihmat-generic-x
M tests/data/acpi/x86/q35/DSDT.acpihmat-noinitiator
M tests/data/acpi/x86/q35/DSDT.applesmc
M tests/data/acpi/x86/q35/DSDT.bridge
M tests/data/acpi/x86/q35/DSDT.core-count
M tests/data/acpi/x86/q35/DSDT.core-count2
M tests/data/acpi/x86/q35/DSDT.cphp
M tests/data/acpi/x86/q35/DSDT.cxl
M tests/data/acpi/x86/q35/DSDT.dimmpxm
M tests/data/acpi/x86/q35/DSDT.ipmibt
M tests/data/acpi/x86/q35/DSDT.ipmismbus
M tests/data/acpi/x86/q35/DSDT.ivrs
M tests/data/acpi/x86/q35/DSDT.memhp
M tests/data/acpi/x86/q35/DSDT.mmio64
M tests/data/acpi/x86/q35/DSDT.multi-bridge
M tests/data/acpi/x86/q35/DSDT.nohpet
M tests/data/acpi/x86/q35/DSDT.numamem
M tests/data/acpi/x86/q35/DSDT.pvpanic-isa
M tests/data/acpi/x86/q35/DSDT.thread-count
M tests/data/acpi/x86/q35/DSDT.thread-count2
M tests/data/acpi/x86/q35/DSDT.tis.tpm12
M tests/data/acpi/x86/q35/DSDT.tis.tpm2
M tests/data/acpi/x86/q35/DSDT.type4-count
M tests/data/acpi/x86/q35/DSDT.viot
M tests/data/acpi/x86/q35/DSDT.xapic
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests: acpi: update expected blobs
_DSM function 7 AML should have followig change:
If ((Arg2 == 0x07))
{
- Local0 = Package (0x02)
- {
- Zero,
- ""
- }
Local2 = AIDX (DerefOf (Arg4 [Zero]), DerefOf (Arg4 [One]
))
- Local0 [Zero] = Local2
+ Local0 = Package (0x02) {}
+ If (!((Local2 == Zero) || (Local2 == 0xFFFFFFFF)))
+ {
+ Local0 [Zero] = Local2
+ Local0 [One] = ""
+ }
+
Return (Local0)
}
}
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <20250115125342.3883374-4-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 1ce979e7269a34d19ea1a65808df014d8b2acbf6
https://github.com/qemu/qemu/commit/1ce979e7269a34d19ea1a65808df014d8b2acbf6
Author: Li Zhijian <lizhijian@fujitsu.com>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M hw/mem/cxl_type3.c
Log Message:
-----------
hw/cxl: Fix msix_notify: Assertion `vector < dev->msix_entries_nr`
This assertion always happens when we sanitize the CXL memory device.
$ echo 1 > /sys/bus/cxl/devices/mem0/security/sanitize
It is incorrect to register an MSIX number beyond the device's capability.
Increase the device's MSIX number to cover the mailbox msix number(9).
Fixes: 43efb0bfad2b ("hw/cxl/mbox: Wire up interrupts for background
completion")
Signed-off-by: Li Zhijian <lizhijian@fujitsu.com>
Message-Id: <20250115075834.167504-1-lizhijian@fujitsu.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 3f65357313e0f928e0bd3ff868b705855d0405bc
https://github.com/qemu/qemu/commit/3f65357313e0f928e0bd3ff868b705855d0405bc
Author: Laurent Vivier <lvivier@redhat.com>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M include/hw/virtio/vhost.h
Log Message:
-----------
vhost: Add stubs for the migration state transfer interface
Migration state transfer interface is only used by vhost-user-fs,
so the interface needs to be defined only when vhost is built.
But I need to use this interface with virtio-net and vhost is not always
enabled, and to avoid undefined reference error during build, define stub
functions for vhost_supports_device_state(), vhost_save_backend_state() and
vhost_load_backend_state().
Cc: Hanna Czenczek <hreitz@redhat.com>
Signed-off-by: Laurent Vivier <lvivier@redhat.com>
Message-Id: <20250115135044.799698-2-lvivier@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 60f543ad917fad731e39ff8ce2ca83b9a9cc9d90
https://github.com/qemu/qemu/commit/60f543ad917fad731e39ff8ce2ca83b9a9cc9d90
Author: Laurent Vivier <lvivier@redhat.com>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M hw/net/virtio-net.c
Log Message:
-----------
virtio-net: vhost-user: Implement internal migration
Add support of VHOST_USER_PROTOCOL_F_DEVICE_STATE in virtio-net
with vhost-user backend.
Cc: Hanna Czenczek <hreitz@redhat.com>
Signed-off-by: Laurent Vivier <lvivier@redhat.com>
Message-Id: <20250115135044.799698-3-lvivier@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 3634039b93cc51816263e0cb5ba32e1b61142d5d
https://github.com/qemu/qemu/commit/3634039b93cc51816263e0cb5ba32e1b61142d5d
Author: David Woodhouse <dwmw@amazon.co.uk>
Date: 2025-01-15 (Wed, 15 Jan 2025)
Changed paths:
M hw/acpi/Kconfig
M hw/acpi/meson.build
A hw/acpi/vmclock.c
M hw/i386/Kconfig
M hw/i386/acpi-build.c
A include/hw/acpi/vmclock.h
A include/standard-headers/linux/vmclock-abi.h
M scripts/update-linux-headers.sh
Log Message:
-----------
hw/acpi: Add vmclock device
The vmclock device addresses the problem of live migration with
precision clocks. The tolerances of a hardware counter (e.g. TSC) are
typically around ±50PPM. A guest will use NTP/PTP/PPS to discipline that
counter against an external source of 'real' time, and track the precise
frequency of the counter as it changes with environmental conditions.
When a guest is live migrated, anything it knows about the frequency of
the underlying counter becomes invalid. It may move from a host where
the counter running at -50PPM of its nominal frequency, to a host where
it runs at +50PPM. There will also be a step change in the value of the
counter, as the correctness of its absolute value at migration is
limited by the accuracy of the source and destination host's time
synchronization.
The device exposes a shared memory region to guests, which can be mapped
all the way to userspace. In the first phase, this merely advertises a
'disruption_marker', which indicates that the guest should throw away any
NTP synchronization it thinks it has, and start again.
Because the region can be exposed all the way to userspace, applications
can still use time from a fast vDSO 'system call', and check the
disruption marker to be sure that their timestamp is indeed truthful.
The structure also allows for the precise time, as known by the host, to
be exposed directly to guests so that they don't have to wait for NTP to
resync from scratch.
The values and fields are based on the nascent virtio-rtc specification,
and the intent is that a version (hopefully precisely this version) of
this structure will be included as an optional part of that spec. In the
meantime, a simple ACPI device along the lines of VMGENID is perfectly
sufficient and is compatible with what's being shipped in certain
commercial hypervisors.
Linux guest support was merged into the 6.13-rc1 kernel:
https://git.kernel.org/torvalds/c/205032724226
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Reviewed-by: Paul Durrant <paul@xen.org>
Message-Id: <07fd5e2f529098ad4d7cab1423fe9f4a03a9cc14.camel@infradead.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Commit: 0e3327b690b76b7c3966b028110ee053cc16a385
https://github.com/qemu/qemu/commit/0e3327b690b76b7c3966b028110ee053cc16a385
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
M MAINTAINERS
M docs/specs/acpi_hest_ghes.rst
M hw/acpi/Kconfig
M hw/acpi/cpu.c
M hw/acpi/generic_event_device.c
M hw/acpi/ghes-stub.c
M hw/acpi/ghes.c
M hw/acpi/meson.build
A hw/acpi/vmclock.c
M hw/arm/virt-acpi-build.c
M hw/display/vhost-user-gpu.c
M hw/display/virtio-gpu-base.c
M hw/i386/Kconfig
M hw/i386/acpi-build.c
M hw/i386/intel_iommu.c
M hw/i386/intel_iommu_internal.h
M hw/i386/pc.c
M hw/mem/cxl_type3.c
M hw/net/virtio-net.c
M hw/pci/msix.c
M hw/pci/pcie.c
M include/hw/acpi/ghes.h
A include/hw/acpi/vmclock.h
M include/hw/i386/intel_iommu.h
M include/hw/virtio/vhost.h
M include/hw/virtio/virtio-gpu.h
A include/standard-headers/linux/vmclock-abi.h
M scripts/update-linux-headers.sh
M target/arm/kvm.c
M tests/data/acpi/x86/pc/DSDT
M tests/data/acpi/x86/pc/DSDT.acpierst
M tests/data/acpi/x86/pc/DSDT.acpihmat
M tests/data/acpi/x86/pc/DSDT.bridge
M tests/data/acpi/x86/pc/DSDT.cphp
M tests/data/acpi/x86/pc/DSDT.dimmpxm
M tests/data/acpi/x86/pc/DSDT.hpbridge
M tests/data/acpi/x86/pc/DSDT.hpbrroot
M tests/data/acpi/x86/pc/DSDT.ipmikcs
M tests/data/acpi/x86/pc/DSDT.memhp
M tests/data/acpi/x86/pc/DSDT.nohpet
M tests/data/acpi/x86/pc/DSDT.numamem
M tests/data/acpi/x86/pc/DSDT.roothp
M tests/data/acpi/x86/q35/DMAR.dmar
M tests/data/acpi/x86/q35/DSDT
M tests/data/acpi/x86/q35/DSDT.acpierst
M tests/data/acpi/x86/q35/DSDT.acpihmat
M tests/data/acpi/x86/q35/DSDT.acpihmat-generic-x
M tests/data/acpi/x86/q35/DSDT.acpihmat-noinitiator
M tests/data/acpi/x86/q35/DSDT.applesmc
M tests/data/acpi/x86/q35/DSDT.bridge
M tests/data/acpi/x86/q35/DSDT.core-count
M tests/data/acpi/x86/q35/DSDT.core-count2
M tests/data/acpi/x86/q35/DSDT.cphp
M tests/data/acpi/x86/q35/DSDT.cxl
M tests/data/acpi/x86/q35/DSDT.dimmpxm
M tests/data/acpi/x86/q35/DSDT.ipmibt
M tests/data/acpi/x86/q35/DSDT.ipmismbus
M tests/data/acpi/x86/q35/DSDT.ivrs
M tests/data/acpi/x86/q35/DSDT.memhp
M tests/data/acpi/x86/q35/DSDT.mmio64
M tests/data/acpi/x86/q35/DSDT.multi-bridge
M tests/data/acpi/x86/q35/DSDT.noacpihp
M tests/data/acpi/x86/q35/DSDT.nohpet
M tests/data/acpi/x86/q35/DSDT.numamem
M tests/data/acpi/x86/q35/DSDT.pvpanic-isa
M tests/data/acpi/x86/q35/DSDT.thread-count
M tests/data/acpi/x86/q35/DSDT.thread-count2
M tests/data/acpi/x86/q35/DSDT.tis.tpm12
M tests/data/acpi/x86/q35/DSDT.tis.tpm2
M tests/data/acpi/x86/q35/DSDT.type4-count
M tests/data/acpi/x86/q35/DSDT.viot
M tests/data/acpi/x86/q35/DSDT.xapic
A tests/qtest/intel-iommu-test.c
M tests/qtest/meson.build
Log Message:
-----------
Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu
into staging
virtio,pc,pci: features, fixes, cleanups
The big thing here are:
stage-1 translation in vtd
internal migration in vhost-user
ghes driver preparation for error injection
new resource uuid feature in virtio gpu
new vmclock device
And as usual, fixes and cleanups.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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# gpg: issuer "mst@redhat.com"
# gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full]
# gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full]
# Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67
# Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469
* tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (49
commits)
hw/acpi: Add vmclock device
virtio-net: vhost-user: Implement internal migration
vhost: Add stubs for the migration state transfer interface
hw/cxl: Fix msix_notify: Assertion `vector < dev->msix_entries_nr`
tests: acpi: update expected blobs
pci: acpi: Windows 'PCI Label Id' bug workaround
tests: acpi: whitelist expected blobs
docs: acpi_hest_ghes: fix documentation for CPER size
acpi/ghes: Change ghes fill logic to work with only one source
acpi/ghes: move offset calculus to a separate function
acpi/ghes: better name the offset of the hardware error firmware
acpi/ghes: rename etc/hardware_error file macros
acpi/ghes: don't crash QEMU if ghes GED is not found
acpi/ghes: better name GHES memory error function
acpi/ghes: make the GHES record generation more generic
acpi/ghes: don't check if physical_address is not zero
acpi/ghes: Change the type for source_id
acpi/ghes: Remove a duplicated out of bounds check
acpi/ghes: Fix acpi_ghes_record_errors() argument
acpi/ghes: better handle source_id and notification
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: 9061ee2a180a7ae24dfea44e2469ce47cc6cd23c
https://github.com/qemu/qemu/commit/9061ee2a180a7ae24dfea44e2469ce47cc6cd23c
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
M hw/intc/loongarch_ipi.c
M hw/intc/loongson_ipi.c
M hw/intc/loongson_ipi_common.c
M hw/loongarch/virt.c
M include/hw/intc/loongarch_ipi.h
M include/hw/intc/loongson_ipi_common.h
M target/loongarch/cpu_helper.c
M target/loongarch/internals.h
M target/loongarch/tcg/tlb_helper.c
Log Message:
-----------
Merge tag 'pull-loongarch-20250116' of https://gitlab.com/bibo-mao/qemu into
staging
loongarch queue
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# gpg: Signature made Wed 15 Jan 2025 20:46:37 EST
# gpg: using EDDSA key 0D8642A3A2659F80B0B3D1A41F7B0C1251ACE7D1
# gpg: Good signature from "bibo mao <maobibo@loongson.cn>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 7044 3A00 19C0 E97A 31C7 13C4 8E86 8FB7 A176 9D4C
# Subkey fingerprint: 0D86 42A3 A265 9F80 B0B3 D1A4 1F7B 0C12 51AC E7D1
* tag 'pull-loongarch-20250116' of https://gitlab.com/bibo-mao/qemu:
hw/intc/loongarch_ipi: Use alternative implemation for cpu_by_arch_id
hw/intc/loongson_ipi: Add more input parameter for cpu_by_arch_id
hw/intc/loongarch_ipi: Remove property num-cpu
hw/intc/loongarch_ipi: Get cpu number from possible_cpu_arch_ids
hw/intc/loongson_ipi: Remove property num_cpu from loongson_ipi_common
hw/intc/loongson_ipi: Remove num_cpu from loongson_ipi_common
hw/intc/loongarch_ipi: Implement realize interface
target/loongarch: Add page table walker support for debugger usage
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Commit: 4d5d933bbc7cc52f6cc6b9021f91fa06266222d5
https://github.com/qemu/qemu/commit/4d5d933bbc7cc52f6cc6b9021f91fa06266222d5
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date: 2025-01-16 (Thu, 16 Jan 2025)
Changed paths:
M hw/block/xen-block.c
M hw/char/xen_console.c
M hw/net/xen_nic.c
M hw/xen/trace-events
M hw/xen/xen-bus-helper.c
M hw/xen/xen-bus.c
M hw/xen/xen_pvdev.c
M include/hw/xen/xen-bus-helper.h
M include/hw/xen/xen-bus.h
M include/system/system.h
M system/runstate.c
Log Message:
-----------
Merge tag 'pull-xenfv-20250116' of git://git.infradead.org/users/dwmw2/qemu
into staging
Xen regression fixes and cleanups
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# Cid8/72lHIgrkZGfpv8BBZkA1XP09vgtUGKyAWm4yHOcB57l8cNiL1nKtqoCLwkQ
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# 2QffxFmskg+A
# =Wz0V
# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 16 Jan 2025 03:40:55 EST
# gpg: using RSA key 314B08ACD0DE481133A5F2869BE980FD0AC01544
# gpg: issuer "dwmw@amazon.co.uk"
# gpg: Good signature from "David Woodhouse <dwmw@amazon.co.uk>" [unknown]
# gpg: aka "David Woodhouse <dwmw@amazon.com>" [unknown]
# gpg: WARNING: The key's User ID is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 314B 08AC D0DE 4811 33A5 F286 9BE9 80FD 0AC0 1544
* tag 'pull-xenfv-20250116' of git://git.infradead.org/users/dwmw2/qemu:
system/runstate: Fix regression, clarify BQL status of exit notifiers
hw/xen: Fix errp handling in xen_console
hw/xen: Use xs_node_read() from xenstore_read_str() instead of open-coding it
hw/xen: Use xs_node_read() from xen_netdev_get_name()
hw/xen: Use xs_node_read() from xen_console_get_name()
hw/xen: Use xs_node_read() from xs_node_vscanf()
xen: do not use '%ms' scanf specifier
hw/xen: Add xs_node_read() helper function
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Compare: https://github.com/qemu/qemu/compare/7433709a1477...4d5d933bbc7c
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