[Qemu-commits] [qemu/qemu] c1bf75: hw/nvram: Add BCM2835 OTP device

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[Qemu-commits] [qemu/qemu] c1bf75: hw/nvram: Add BCM2835 OTP device

From:	Richard Henderson
Subject:	[Qemu-commits] [qemu/qemu] c1bf75: hw/nvram: Add BCM2835 OTP device
Date:	Mon, 01 Jul 2024 10:47:36 -0700
  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: c1bf754041f4a9101059c0151475ed69df1c7e2e
      
https://github.com/qemu/qemu/commit/c1bf754041f4a9101059c0151475ed69df1c7e2e
  Author: Rayhan Faizel <rayhan.faizel@gmail.com>
  Date:   2024-07-01 (Mon, 01 Jul 2024)

  Changed paths:
    A hw/nvram/bcm2835_otp.c
    M hw/nvram/meson.build
    A include/hw/nvram/bcm2835_otp.h

  Log Message:
  -----------
  hw/nvram: Add BCM2835 OTP device

The OTP device registers are currently stubbed. For now, the device
houses the OTP rows which will be accessed directly by other peripherals.

Signed-off-by: Rayhan Faizel <rayhan.faizel@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 6bf7993921827817eb313f44509bf4ba7ebf88bb
      
https://github.com/qemu/qemu/commit/6bf7993921827817eb313f44509bf4ba7ebf88bb
  Author: Rayhan Faizel <rayhan.faizel@gmail.com>
  Date:   2024-07-01 (Mon, 01 Jul 2024)

  Changed paths:
    M hw/arm/bcm2835_peripherals.c
    M include/hw/arm/bcm2835_peripherals.h

  Log Message:
  -----------
  hw/arm: Connect OTP device to BCM2835

Replace stubbed OTP memory region with the new OTP device.

Signed-off-by: Rayhan Faizel <rayhan.faizel@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 5d5f1b60916aa6bbebe192d74acb762414377430
      
https://github.com/qemu/qemu/commit/5d5f1b60916aa6bbebe192d74acb762414377430
  Author: Rayhan Faizel <rayhan.faizel@gmail.com>
  Date:   2024-07-01 (Mon, 01 Jul 2024)

  Changed paths:
    M hw/arm/bcm2835_peripherals.c
    M hw/misc/bcm2835_property.c
    M include/hw/arm/raspberrypi-fw-defs.h
    M include/hw/misc/bcm2835_property.h

  Log Message:
  -----------
  hw/misc: Implement mailbox properties for customer OTP and device specific 
private keys

Four mailbox properties are implemented as follows:
1. Customer OTP: GET_CUSTOMER_OTP and SET_CUSTOMER_OTP
2. Device-specific private key: GET_PRIVATE_KEY and
SET_PRIVATE_KEY.

The customer OTP is located in the rows 36-43. The device-specific private key
is located in the rows 56-63.

The customer OTP can be locked with the magic numbers 0xffffffff 0xaffe0000
when running the SET_CUSTOMER_OTP mailbox command. Bit 6 of row 32 indicates
this lock, which is undocumented. The lock also applies to the device-specific
private key.

Signed-off-by: Rayhan Faizel <rayhan.faizel@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 24a7cd6a7c21f82f1ce9bd5ecf6fb54eb7bf4602
      
https://github.com/qemu/qemu/commit/24a7cd6a7c21f82f1ce9bd5ecf6fb54eb7bf4602
  Author: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
  Date:   2024-07-01 (Mon, 01 Jul 2024)

  Changed paths:
    M tests/avocado/machine_aarch64_sbsaref.py

  Log Message:
  -----------
  tests/avocado: update firmware for sbsa-ref

Update firmware to have graphics card memory fix from EDK2 commit
c1d1910be6e04a8b1a73090cf2881fb698947a6e:

    OvmfPkg/QemuVideoDxe: add feature PCD to remap framebuffer W/C

    Some platforms (such as SBSA-QEMU on recent builds of the emulator) only
    tolerate misaligned accesses to normal memory, and raise alignment
    faults on such accesses to device memory, which is the default for PCIe
    MMIO BARs.

    When emulating a PCIe graphics controller, the framebuffer is typically
    exposed via a MMIO BAR, while the disposition of the region is closer to
    memory (no side effects on reads or writes, except for the changing
    picture on the screen; direct random access to any pixel in the image).

    In order to permit the use of such controllers on platforms that only
    tolerate these types of accesses for normal memory, it is necessary to
    remap the memory. Use the DXE services to set the desired capabilities
    and attributes.

    Hide this behavior under a feature PCD so only platforms that really
    need it can enable it. (OVMF on x86 has no need for this)

With this fix enabled we can boot sbsa-ref with more than one cpu core.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240620-b4-new-firmware-v3-1-29a3a2f1be1e@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 6c84daac58f0d75a908626faf89a832fc0532140
      
https://github.com/qemu/qemu/commit/6c84daac58f0d75a908626faf89a832fc0532140
  Author: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
  Date:   2024-07-01 (Mon, 01 Jul 2024)

  Changed paths:
    M tests/avocado/machine_aarch64_sbsaref.py

  Log Message:
  -----------
  tests/avocado: use default amount of cores on sbsa-ref

The version of the sbsa-ref EDK2 firmware we used to use in this test
had a bug where it might make an unaligned access to the framebuffer,
which causes a guest crash on newer versions of QEMU where we enforce
the architectural requirement that unaligned accesses to Device memory
should take an exception.

We happened to not notice this because our test was booting with "-smp
1" and through luck this didn't write the boot logo to the framebuffer
at an unaligned address; but trying to boot the same firmware with two
CPUs would result in a guest crash. Now we have updated the firmware
we're using for the test, we can make the test use all the cores on the
board, so we are testing the SMP boot path.

Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240620-b4-new-firmware-v3-2-29a3a2f1be1e@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 69970205edb661f79a7f6d6046785c521c6da80b
      
https://github.com/qemu/qemu/commit/69970205edb661f79a7f6d6046785c521c6da80b
  Author: Nicolin Chen <nicolinc@nvidia.com>
  Date:   2024-07-01 (Mon, 01 Jul 2024)

  Changed paths:
    M hw/arm/smmu-common.c
    M hw/arm/smmuv3.c
    M include/hw/arm/smmu-common.h

  Log Message:
  -----------
  hw/arm/smmu-common: Replace smmu_iommu_mr with smmu_find_sdev

The caller of smmu_iommu_mr wants to get sdev for smmuv3_flush_config().

Do it directly instead of bridging with an iommu mr pointer.

Signed-off-by: Nicolin Chen <nicolinc@nvidia.com>
Message-id: 20240619002218.926674-1-nicolinc@nvidia.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 76bccf3cb9d9383da0128bbc6d1300cddbe3ae8f
      
https://github.com/qemu/qemu/commit/76bccf3cb9d9383da0128bbc6d1300cddbe3ae8f
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-07-01 (Mon, 01 Jul 2024)

  Changed paths:
    M target/arm/tcg/vec_helper.c

  Log Message:
  -----------
  target/arm: Fix VCMLA Dd, Dn, Dm[idx]

The inner loop, bounded by eltspersegment, must not be
larger than the outer loop, bounded by elements.

Cc: qemu-stable@nongnu.org
Fixes: 18fc2405781 ("target/arm: Implement SVE fp complex multiply add 
(indexed)")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2376
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240625183536.1672454-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: a5b72ccc0f21183e7863745b0d82f144ecfb59f5
      
https://github.com/qemu/qemu/commit/a5b72ccc0f21183e7863745b0d82f144ecfb59f5
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-07-01 (Mon, 01 Jul 2024)

  Changed paths:
    M target/arm/tcg/vec_helper.c

  Log Message:
  -----------
  target/arm: Fix SQDMULH (by element) with Q=0

The inner loop, bounded by eltspersegment, must not be
larger than the outer loop, bounded by elements.

Cc: qemu-stable@nongnu.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240625183536.1672454-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 7619129f0d4a14d918227c5c47ad7433662e9ccc
      
https://github.com/qemu/qemu/commit/7619129f0d4a14d918227c5c47ad7433662e9ccc
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-07-01 (Mon, 01 Jul 2024)

  Changed paths:
    M target/arm/vfp_helper.c
    M tests/tcg/aarch64/Makefile.target
    A tests/tcg/aarch64/test-2375.c

  Log Message:
  -----------
  target/arm: Fix FJCVTZS vs flush-to-zero

Input denormals cause the Javascript inexact bit
(output to Z) to be set.

Cc: qemu-stable@nongnu.org
Fixes: 6c1f6f2733a ("target/arm: Implement ARMv8.3-JSConv")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2375
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240625183536.1672454-4-richard.henderson@linaro.org
[PMM: fixed hardcoded tab in test case]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: f698e4527064da714859892ba49d25a0a2afd12d
      
https://github.com/qemu/qemu/commit/f698e4527064da714859892ba49d25a0a2afd12d
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-07-01 (Mon, 01 Jul 2024)

  Changed paths:
    M target/arm/helper.h
    M target/arm/tcg/a64.decode
    M target/arm/tcg/translate-a64.c
    M target/arm/tcg/vec_helper.c

  Log Message:
  -----------
  target/arm: Convert SQRDMLAH, SQRDMLSH to decodetree

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240625183536.1672454-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 65dd60a65b83191c14ad2c144a2c189b6eb00b46
      
https://github.com/qemu/qemu/commit/65dd60a65b83191c14ad2c144a2c189b6eb00b46
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-07-01 (Mon, 01 Jul 2024)

  Changed paths:
    M target/arm/tcg/a64.decode
    M target/arm/tcg/translate-a64.c

  Log Message:
  -----------
  target/arm: Convert SDOT, UDOT to decodetree

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240625183536.1672454-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 849b7c1661d1784dad4bb56998ba8952d2c8a5d1
      
https://github.com/qemu/qemu/commit/849b7c1661d1784dad4bb56998ba8952d2c8a5d1
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-07-01 (Mon, 01 Jul 2024)

  Changed paths:
    M target/arm/tcg/a64.decode
    M target/arm/tcg/translate-a64.c

  Log Message:
  -----------
  target/arm: Convert SUDOT, USDOT to decodetree

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240625183536.1672454-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 9130827c4c7976a52dcc70db8beb699a200c35a3
      
https://github.com/qemu/qemu/commit/9130827c4c7976a52dcc70db8beb699a200c35a3
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-07-01 (Mon, 01 Jul 2024)

  Changed paths:
    M target/arm/tcg/a64.decode
    M target/arm/tcg/translate-a64.c

  Log Message:
  -----------
  target/arm: Convert BFDOT to decodetree

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240625183536.1672454-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 1c6ecab43172b9a5c345df38de5e8b4fb5c285e1
      
https://github.com/qemu/qemu/commit/1c6ecab43172b9a5c345df38de5e8b4fb5c285e1
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-07-01 (Mon, 01 Jul 2024)

  Changed paths:
    M target/arm/tcg/a64.decode
    M target/arm/tcg/translate-a64.c

  Log Message:
  -----------
  target/arm: Convert BFMLALB, BFMLALT to decodetree

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240625183536.1672454-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 9676c9d9b5a937e432118de8070261648fe14706
      
https://github.com/qemu/qemu/commit/9676c9d9b5a937e432118de8070261648fe14706
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-07-01 (Mon, 01 Jul 2024)

  Changed paths:
    M target/arm/tcg/a64.decode
    M target/arm/tcg/translate-a64.c

  Log Message:
  -----------
  target/arm: Convert BFMMLA, SMMLA, UMMLA, USMMLA to decodetree

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240625183536.1672454-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 6515b13e87c83f8c3a9f6ad5e6a3f45ba31c70ca
      
https://github.com/qemu/qemu/commit/6515b13e87c83f8c3a9f6ad5e6a3f45ba31c70ca
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-07-01 (Mon, 01 Jul 2024)

  Changed paths:
    M target/arm/tcg/translate-a64.c

  Log Message:
  -----------
  target/arm: Add data argument to do_fp3_vector

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240625183536.1672454-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 0f46ebee6318238c375df35c0c0f56d04f075c50
      
https://github.com/qemu/qemu/commit/0f46ebee6318238c375df35c0c0f56d04f075c50
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-07-01 (Mon, 01 Jul 2024)

  Changed paths:
    M target/arm/tcg/a64.decode
    M target/arm/tcg/translate-a64.c

  Log Message:
  -----------
  target/arm: Convert FCADD to decodetree

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240625183536.1672454-12-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 80b02a565e518414ba3ced137571ed4597595082
      
https://github.com/qemu/qemu/commit/80b02a565e518414ba3ced137571ed4597595082
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-07-01 (Mon, 01 Jul 2024)

  Changed paths:
    M target/arm/tcg/a64.decode
    M target/arm/tcg/translate-a64.c

  Log Message:
  -----------
  target/arm: Convert FCMLA to decodetree

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240625183536.1672454-13-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 2cd5078d5784ef57935d2b157bf6d5566e86eac9
      
https://github.com/qemu/qemu/commit/2cd5078d5784ef57935d2b157bf6d5566e86eac9
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-07-01 (Mon, 01 Jul 2024)

  Changed paths:
    M target/arm/tcg/translate-a64.c

  Log Message:
  -----------
  target/arm: Delete dead code from disas_simd_indexed

MLA, MLS, SQDMULH, SQRDMULH, were converted with 8db93dcd3def
and f80701cb44d, and this code should have been removed then.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240625183536.1672454-14-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 4df378ab5164635d0431086b800adb770c037a64
      
https://github.com/qemu/qemu/commit/4df378ab5164635d0431086b800adb770c037a64
  Author: Gustavo Romero <gustavo.romero@linaro.org>
  Date:   2024-07-01 (Mon, 01 Jul 2024)

  Changed paths:
    M target/arm/tcg/cpu64.c

  Log Message:
  -----------
  target/arm: Fix indentation

Fix comment indentation adding a missing space.

Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240624180915.4528-2-gustavo.romero@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: c5f9e8bb9300d0cae42d2cb19f6a4d340813f8b5
      
https://github.com/qemu/qemu/commit/c5f9e8bb9300d0cae42d2cb19f6a4d340813f8b5
  Author: Gustavo Romero <gustavo.romero@linaro.org>
  Date:   2024-07-01 (Mon, 01 Jul 2024)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/tcg/cpu32.c

  Log Message:
  -----------
  target/arm: Move initialization of debug ID registers

Move the initialization of the debug ID registers to aa32_max_features,
which is used to set the 32-bit ID registers. This ensures that the
debug ID registers are consistently set for the max CPU in a single
place.

Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240624180915.4528-3-gustavo.romero@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 02ff2add77099f9deb7d6a18c9b4110572771f6a
      
https://github.com/qemu/qemu/commit/02ff2add77099f9deb7d6a18c9b4110572771f6a
  Author: Gustavo Romero <gustavo.romero@linaro.org>
  Date:   2024-07-01 (Mon, 01 Jul 2024)

  Changed paths:
    M docs/system/arm/emulation.rst
    M target/arm/tcg/cpu32.c
    M target/arm/tcg/cpu64.c

  Log Message:
  -----------
  target/arm: Enable FEAT_Debugv8p8 for -cpu max

Enable FEAT_Debugv8p8 for max CPU. This feature is out of scope for QEMU
since it concerns the external debug interface for JTAG, but is
mandatory in Armv8.8 implementations, hence it is reported as supported
in the ID registers.

Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240624180915.4528-4-gustavo.romero@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 6529511a8412a54afbcad850a62c0f39b4a9fc6c
      
https://github.com/qemu/qemu/commit/6529511a8412a54afbcad850a62c0f39b4a9fc6c
  Author: Patrick Leis <venture@google.com>
  Date:   2024-07-01 (Mon, 01 Jul 2024)

  Changed paths:
    M MAINTAINERS

  Log Message:
  -----------
  MAINTAINERS: Update my family name

Signed-off-by: Patrick Leis <venture@google.com>
Message-id: 20240626211623.3510701-1-venture@google.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 247f24507f78ed80314b6bd474db8ae1ac7c0253
      
https://github.com/qemu/qemu/commit/247f24507f78ed80314b6bd474db8ae1ac7c0253
  Author: Sai Pavan Boddu <sai.pavan.boddu@amd.com>
  Date:   2024-07-01 (Mon, 01 Jul 2024)

  Changed paths:
    M hw/misc/zynq_slcr.c

  Log Message:
  -----------
  hw/misc/zynq_slcr: Add boot-mode property

boot-mode property sets user values into BOOT_MODE register, on hardware
these are derived from board switches.

Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@amd.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
Message-id: 20240621125906.1300995-2-sai.pavan.boddu@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 7df3747c92d13a56ddfd8b8fdec06c7c6fddfd66
      
https://github.com/qemu/qemu/commit/7df3747c92d13a56ddfd8b8fdec06c7c6fddfd66
  Author: Sai Pavan Boddu <sai.pavan.boddu@amd.com>
  Date:   2024-07-01 (Mon, 01 Jul 2024)

  Changed paths:
    M hw/arm/xilinx_zynq.c

  Log Message:
  -----------
  hw/arm/xilinx_zynq: Add boot-mode property

Read boot-mode value as machine property and propagate that to
SLCR.BOOT_MODE register.

Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@amd.com>
Acked-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
Message-id: 20240621125906.1300995-3-sai.pavan.boddu@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 2d30506d065743008184a3b0269529bd9159560e
      
https://github.com/qemu/qemu/commit/2d30506d065743008184a3b0269529bd9159560e
  Author: Sai Pavan Boddu <sai.pavan.boddu@amd.com>
  Date:   2024-07-01 (Mon, 01 Jul 2024)

  Changed paths:
    M MAINTAINERS
    A docs/system/arm/xlnx-zynq.rst
    M docs/system/target-arm.rst

  Log Message:
  -----------
  docs/system/arm: Add a doc for zynq board

Added the supported device list and an example command.

Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@amd.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
Message-id: 20240621125906.1300995-4-sai.pavan.boddu@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 7d9b3c34f30045eb50d1c890be46bfde4100bf65
      
https://github.com/qemu/qemu/commit/7d9b3c34f30045eb50d1c890be46bfde4100bf65
  Author: Inès Varhol <ines.varhol@telecom-paris.fr>
  Date:   2024-07-01 (Mon, 01 Jul 2024)

  Changed paths:
    M tests/qtest/stm32l4x5_syscfg-test.c

  Log Message:
  -----------
  tests/qtest: Fix STM32L4x5 SYSCFG irq line 15 state assumption

The QTest `test_irq_pin_multiplexer` makes the assumption that the
reset state of irq line 15 is low, which is false since STM32L4x5 GPIO
was implemented (the reset state of pin GPIOA15 is high because there's
pull-up and it results in the irq line 15 also being high at reset).

It wasn't triggering an error because `test_interrupt` was mistakenly
"resetting" the line low.

This commit corrects these two mistakes by :
- not setting the line low in `test_interrupt`
- using an irq line in `test_irq_pin_multiplexer` which is low at reset

Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Message-id: 20240629104454.366283-1-ines.varhol@telecom-paris.fr
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 9c4887e3b68a362f2f5a4e86daab98a51b3b769e
      
https://github.com/qemu/qemu/commit/9c4887e3b68a362f2f5a4e86daab98a51b3b769e
  Author: Inès Varhol <ines.varhol@telecom-paris.fr>
  Date:   2024-07-01 (Mon, 01 Jul 2024)

  Changed paths:
    M hw/misc/stm32l4x5_exti.c
    M include/hw/misc/stm32l4x5_exti.h

  Log Message:
  -----------
  hw/misc: In STM32L4x5 EXTI, correct configurable interrupts

The implementation of configurable interrupts (interrupts supporting
edge selection) was incorrectly expecting alternating input levels :
this commits adds a new status field `irq_levels` to actually detect
edges.

Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Message-id: 20240629110800.539969-2-ines.varhol@telecom-paris.fr
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 58c782de557beb496bfb4c5ade721bbbd2480c72
      
https://github.com/qemu/qemu/commit/58c782de557beb496bfb4c5ade721bbbd2480c72
  Author: Inès Varhol <ines.varhol@telecom-paris.fr>
  Date:   2024-07-01 (Mon, 01 Jul 2024)

  Changed paths:
    M tests/qtest/stm32l4x5_exti-test.c
    M tests/qtest/stm32l4x5_syscfg-test.c

  Log Message:
  -----------
  tests/qtest: Ensure STM32L4x5 EXTI state is correct at the end of QTests

EXTI's new field `irq_levels` tracks irq levels between tests when using
`global_qtest`.
This happens in `stm32l4x5_exti-test.c`, `stm32l4x5_syscfg-test.c` and
`stm32l4x5_gpio-test.c` (`dm163.c` doesn't use `global_qtest`).

To ensure that `irq_levels` has the same value before and after each
QTest, this commit toggles back the irq lines that were changed at the
end of each problematic test. Most QTests were already doing this.

Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr>
Message-id: 20240629110800.539969-3-ines.varhol@telecom-paris.fr
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: c80a339587fe4148292c260716482dd2f86d4476
      
https://github.com/qemu/qemu/commit/c80a339587fe4148292c260716482dd2f86d4476
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-07-01 (Mon, 01 Jul 2024)

  Changed paths:
    M MAINTAINERS
    M docs/system/arm/emulation.rst
    A docs/system/arm/xlnx-zynq.rst
    M docs/system/target-arm.rst
    M hw/arm/bcm2835_peripherals.c
    M hw/arm/smmu-common.c
    M hw/arm/smmuv3.c
    M hw/arm/xilinx_zynq.c
    M hw/misc/bcm2835_property.c
    M hw/misc/stm32l4x5_exti.c
    M hw/misc/zynq_slcr.c
    A hw/nvram/bcm2835_otp.c
    M hw/nvram/meson.build
    M include/hw/arm/bcm2835_peripherals.h
    M include/hw/arm/raspberrypi-fw-defs.h
    M include/hw/arm/smmu-common.h
    M include/hw/misc/bcm2835_property.h
    M include/hw/misc/stm32l4x5_exti.h
    A include/hw/nvram/bcm2835_otp.h
    M target/arm/cpu.h
    M target/arm/helper.h
    M target/arm/tcg/a64.decode
    M target/arm/tcg/cpu32.c
    M target/arm/tcg/cpu64.c
    M target/arm/tcg/translate-a64.c
    M target/arm/tcg/vec_helper.c
    M target/arm/vfp_helper.c
    M tests/avocado/machine_aarch64_sbsaref.py
    M tests/qtest/stm32l4x5_exti-test.c
    M tests/qtest/stm32l4x5_syscfg-test.c
    M tests/tcg/aarch64/Makefile.target
    A tests/tcg/aarch64/test-2375.c

  Log Message:
  -----------
  Merge tag 'pull-target-arm-20240701' of 
https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * tests/avocado: update firmware for sbsa-ref and use all cores
 * hw/arm/smmu-common: Replace smmu_iommu_mr with smmu_find_sdev
 * arm: Fix VCMLA Dd, Dn, Dm[idx]
 * arm: Fix SQDMULH (by element) with Q=0
 * arm: Fix FJCVTZS vs flush-to-zero
 * arm: More conversion of A64 AdvSIMD to decodetree
 * arm: Enable FEAT_Debugv8p8 for -cpu max
 * MAINTAINERS: Update family name for Patrick Leis
 * hw/arm/xilinx_zynq: Add boot-mode property
 * docs/system/arm: Add a doc for zynq board
 * hw/misc: In STM32L4x5 EXTI, correct configurable interrupts
 * tests/qtest: fix minor issues in STM32L4x5 tests

# -----BEGIN PGP SIGNATURE-----
#
# iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmaC1BMZHHBldGVyLm1h
# eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3nDOEACCoewjO2FJ4RFXMSmgr0Zf
# jxWliu7osw7oeG4ZNq1+xMiXeW0vyS54eW41TMki1f98N/yK8v55BM8kBBvDvZaz
# R5DUXpN+MtwD9A62md3B2c4mFXHqk1UOGbKi4btbtFj4lS8pV51mPmApzBUr2iTj
# w6dCLciLOt87NWgtLECXsZ3evn+VlTRc+Hmfp1M/C/Rf2Qx3zis/CFHGQsZLGwzG
# 2WhTpU1BKeOfsQa1VbSX6un14d72/JATFZN3rSgMbOEbvsCEeP+rnkzX57ejGyxV
# 4DUx69gEAqS5bOfkQHLwy82WsunD/oIgp+GpYaYgINHzh6UkEsPoymrHAaPgV1Vh
# g0TaBtbv2p89RFY1C2W2Mi4ICQ14a+oIV9FPvDsOE8Wq+wDAy/ZxZs7G6flxqods
# s4JvcMqB3kUNBZaMsFVXTKdqT1PufICS+gx0VsKdKDwXcOHwMS10nTlEOPzqvoBA
# phAsEbjnjWVhf03XTfCus+l5NT96lswCzPcUovb3CitSc2A1KUye3TyzHnxIqmOt
# Owcl+Oiso++cgYzr/BCveTAYKYoRZzVcq5jCl4bBUH/8sLrRDbT0cpFpcMk72eE9
# VhR00kbkDfL3nKrulLsG8FeUlisX5+oGb3G5AdPtU9sqJPJMmBGaF+KniI0wi7VN
# 5teHq08upLMF5JAjiKzZIA==
# =faXD
# -----END PGP SIGNATURE-----
# gpg: Signature made Mon 01 Jul 2024 09:06:43 AM PDT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" 
[full]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [unknown]

* tag 'pull-target-arm-20240701' of 
https://git.linaro.org/people/pmaydell/qemu-arm: (29 commits)
  tests/qtest: Ensure STM32L4x5 EXTI state is correct at the end of QTests
  hw/misc: In STM32L4x5 EXTI, correct configurable interrupts
  tests/qtest: Fix STM32L4x5 SYSCFG irq line 15 state assumption
  docs/system/arm: Add a doc for zynq board
  hw/arm/xilinx_zynq: Add boot-mode property
  hw/misc/zynq_slcr: Add boot-mode property
  MAINTAINERS: Update my family name
  target/arm: Enable FEAT_Debugv8p8 for -cpu max
  target/arm: Move initialization of debug ID registers
  target/arm: Fix indentation
  target/arm: Delete dead code from disas_simd_indexed
  target/arm: Convert FCMLA to decodetree
  target/arm: Convert FCADD to decodetree
  target/arm: Add data argument to do_fp3_vector
  target/arm: Convert BFMMLA, SMMLA, UMMLA, USMMLA to decodetree
  target/arm: Convert BFMLALB, BFMLALT to decodetree
  target/arm: Convert BFDOT to decodetree
  target/arm: Convert SUDOT, USDOT to decodetree
  target/arm: Convert SDOT, UDOT to decodetree
  target/arm: Convert SQRDMLAH, SQRDMLSH to decodetree
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Compare: https://github.com/qemu/qemu/compare/1152a0414944...c80a339587fe

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