[Qemu-commits] [qemu/qemu] 62c5bc: hw/riscv: handle 32 bit CPUs kernel

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[Qemu-commits] [qemu/qemu] 62c5bc: hw/riscv: handle 32 bit CPUs kernel_e

From:	Peter Maydell
Subject:	[Qemu-commits] [qemu/qemu] 62c5bc: hw/riscv: handle 32 bit CPUs kernel_entry in riscv...
Date:	Tue, 21 Feb 2023 07:56:15 -0800
  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 62c5bc348e39f8b715fb2eac414749ee7e630043
      
https://github.com/qemu/qemu/commit/62c5bc348e39f8b715fb2eac414749ee7e630043
  Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
  Date:   2023-02-16 (Thu, 16 Feb 2023)

  Changed paths:
    M hw/riscv/boot.c
    M hw/riscv/microchip_pfsoc.c
    M hw/riscv/opentitan.c
    M hw/riscv/sifive_e.c
    M hw/riscv/sifive_u.c
    M hw/riscv/spike.c
    M hw/riscv/virt.c
    M include/hw/riscv/boot.h

  Log Message:
  -----------
  hw/riscv: handle 32 bit CPUs kernel_entry in riscv_load_kernel()

Next patch will move all calls to riscv_load_initrd() to
riscv_load_kernel(). Machines that want to load initrd will be able to
do via an extra flag to riscv_load_kernel().

This change will expose a sign-extend behavior that is happening in
load_elf_ram_sym() when running 32 bit guests [1]. This is currently
obscured by the fact that riscv_load_initrd() is using the return of
riscv_load_kernel(), defined as target_ulong, and this return type will
crop the higher 32 bits that would be padded with 1s by the sign
extension when running in 32 bit targets. The changes to be done will
force riscv_load_initrd() to use an uint64_t instead, exposing it to the
padding when dealing with 32 bit CPUs.

There is a discussion about whether load_elf_ram_sym() should or should
not sign extend the value returned by 'lowaddr'. What we can do is to
prevent the behavior change that the next patch will end up doing.
riscv_load_initrd() wasn't dealing with 64 bit kernel entries when
running 32 bit CPUs, and we want to keep it that way.

One way of doing it is to use target_ulong in 'kernel_entry' in
riscv_load_kernel() and rely on the fact that this var will not be sign
extended for 32 bit targets. Another way is to explictly clear the
higher 32 bits when running 32 bit CPUs for all possibilities of
kernel_entry.

We opted for the later. This will allow us to be clear about the design
choices made in the function, while also allowing us to add a small
comment about what load_elf_ram_sym() is doing. With this change, the
consolation patch can do its job without worrying about unintended
behavioral changes.

[1] https://lists.gnu.org/archive/html/qemu-devel/2023-01/msg02281.html

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230206140022.2748401-2-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>


  Commit: 487d73fc470d233f2d5da9cec7cd229ae8b88b49
      
https://github.com/qemu/qemu/commit/487d73fc470d233f2d5da9cec7cd229ae8b88b49
  Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
  Date:   2023-02-16 (Thu, 16 Feb 2023)

  Changed paths:
    M hw/riscv/boot.c
    M hw/riscv/microchip_pfsoc.c
    M hw/riscv/opentitan.c
    M hw/riscv/sifive_e.c
    M hw/riscv/sifive_u.c
    M hw/riscv/spike.c
    M hw/riscv/virt.c
    M include/hw/riscv/boot.h

  Log Message:
  -----------
  hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel()

The microchip_icicle_kit, sifive_u, spike and virt boards are now doing
the same steps when '-kernel' is used:

- execute load_kernel()
- load init_rd()
- write kernel_cmdline

Let's fold everything inside riscv_load_kernel() to avoid code
repetition. To not change the behavior of boards that aren't calling
riscv_load_init(), add an 'load_initrd' flag to riscv_load_kernel() and
allow these boards to opt out from initrd loading.

Cc: Palmer Dabbelt <palmer@dabbelt.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230206140022.2748401-3-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>


  Commit: 8b64475bd529ffe42f89b6c2f819e5133c9f8317
      
https://github.com/qemu/qemu/commit/8b64475bd529ffe42f89b6c2f819e5133c9f8317
  Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
  Date:   2023-02-16 (Thu, 16 Feb 2023)

  Changed paths:
    M hw/riscv/boot.c
    M include/hw/riscv/boot.h

  Log Message:
  -----------
  hw/riscv/boot.c: make riscv_load_initrd() static

The only remaining caller is riscv_load_kernel_and_initrd() which
belongs to the same file.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230206140022.2748401-4-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>


  Commit: 952575b7fcaeee820d5fde5bd7113db983873d65
      
https://github.com/qemu/qemu/commit/952575b7fcaeee820d5fde5bd7113db983873d65
  Author: Bin Meng <bmeng@tinylab.org>
  Date:   2023-02-16 (Thu, 16 Feb 2023)

  Changed paths:
    M pc-bios/opensbi-riscv32-generic-fw_dynamic.bin
    M pc-bios/opensbi-riscv64-generic-fw_dynamic.bin
    M roms/opensbi

  Log Message:
  -----------
  roms/opensbi: Upgrade from v1.1 to v1.2

Upgrade OpenSBI from v1.1 to v1.2 and the pre-built bios images.

The v1.2 release includes the following commits:

994c8cf lib: sbi_timer: Added a conditional wait function which can timeout
caa5eea lib: sbi: add check for ipi device for hsm start
0374ccf lib: sbi_hart: Shorten the code to set MPV bit
4e21cca lib: utils/serial: Update Shakti UART based on latest implementation
88b790f lib: sbi: Fix sbi_snprintf
1545afd lib: sbi: Fix counter index sanity check
83db3af lib: sbi: Add the bound check for events during config match
860a376 lib: sbi: Fix possible buffer overrun in counter validation
11c0008 lib: sbi: Fix fw_event_map initialization
8e86b23 lib: utils/fdt: Factor out common uart node code
7d28d3b lib: utils/serial: Initialize platform_uart_data to zero
7198e1d lib: serial: Clean up coding style in sifive-uart.c
f272035 lib: utils/serial: Ensure baudrate is non-zero before using
b9edf49 lib: sbi: Fix printf handling of long long
422f0e0 scripts: Add Kconfiglib v14.1.0 under scripts directory
662e631 Makefile: Add initial kconfig support for each platform
de80e93 Makefile: Compile lib/utils sources separately for each platform
26bbff5 lib: utils/serial: Use kconfig for enabling/disabling drivers
2adc94b lib: utils/reset: Use kconfig for enabling/disabling drivers
3e76a60 lib: utils/sys: Use kconfig for enabling/disabling drivers
013dbb3 lib: utils/timer: Use kconfig for enabling/disabling drivers
76af9d4 lib: utils/ipi: Use kconfig for enabling/disabling drivers
0b1cf2f lib: utils/irqchip: Use kconfig for enabling/disabling drivers
b126ce4 lib: utils/i2c: Use kconfig for enabling/disabling drivers
5616aa4 lib: utils/gpio: Use kconfig for enabling/disabling drivers
68d7b85 lib: utils/fdt: Use kconfig for enabling/disabling
d514a8f platform: generic: Use kconfig for enabling/disabling overrides
bc317a3 platform: generic: Use kconfig to set platform version and default name
eccb9df platform: Remove redundant config.mk from all platforms
0723bab docs: Update documentation for kconfig support
a6a8557 Makefile: Fix typo related to object.mk
9529e36 include: Add mstatus[h].GVA encodings
1fbe777 lib: sbi_trap: Save mstatus[h].GVA in trap->gva
1c4ce74 lib: sbi: Set gva when creating sbi_trap_info
5a0ca09 lib: sbi_trap: Set hypervisor CSRs for HS-mode
a69eb6c lib: sbi_trap: Set hstatus.GVA when going to HS-mode
111afc1 lib: sbi_illegal_insn: Fix FENCE.TSO emulation infinite trap loop
adf44b5 lib: sbi: Use the official extension name for AIA M-mode CSRs
cbaa9b0 lib: utils: serial: Add Cadence UART driver
622cc5f include: Remove sideleg and sedeleg
a90cf6b lib: sbi_pmu: Remove "event_idx" member from struct sbi_pmu_fw_event
1664d0e lib: sbi_pmu: Replace sbi_pmu_ctr_read() with sbi_pmu_ctr_fw_read()
e238459 lib: sbi_pmu: Firmware counters are always 64 bits wide
c9b388d lib: sbi_pmu: Simplify FW counters to reduce memory usage
d10c1f4 lib: sbi_pmu: Add custom PMU device operations
ee69f8e lib: sbi: Print platform PMU device at boot-time
5019fd1 include: sbi: Reduce includes in sbi_pmu.h
d32b0a9 docs: pmu: fix Unmatched example typo
19664f6 docs: pmu: extend bindings example for Unmatched
37a0d83 lib: sbi_trap: Add helper to get GVA in sbi_trap_regs
46e744a lib: sbi_misaligned_ldst: Set GVA if not emulating
8ce486a lib: utils/fdt: Fix DT parsing in fdt_pmu_setup()
49372f2 lib: sbi: Fix sbi_strnlen wrong count decrement
7f09fba lib: utils/serial: add semihosting support
7105c18 docs/firmware: Update FW_JUMP documentation
3f3d401 docs: Fix some typos
e54cb32 lib: sbi_pmu: move pmu irq information into pmu itself
c316fa3 lib: sbi_hart: move hart_features struct to a public location
4f2acb5 lib: sbi_platform: expose hart_features to extension_init callback
2f63f24 platform: generic: add extensions_init handler and platform-override
b6e520b platform: generic: allwinner: add support for c9xx pmu
98aa127 include: sbi: Fix typo in comment
11d14ae lib: sbi: Fix typo in comment
60b78fe include: sbi: Fix grammar in comment
dcdaf30 lib: sbi: Add sbi_domain_root_add_memrange() API
bd7ef41 platform: andes/ae350: Remove enabling cache from an350_final_init
9899b59 platform: andes/ae350: Use kconfig to set platform version and default 
name
88f58a3 platform: andes/ae350: Use fdt serial driver
ef9f02e lib: utils/timer: Add Andes fdt timer support
8234fc1 lib: utils/reset: Add Andes fdt reset driver support
127a3f2 platform: andes/ae350: Use fdt irqchip driver
6f3258e platform: andes/ae350: Add fw_platform_init for platform initialization
ce7c490 lib: utils/ipi: Add Andes fdt ipi driver support
c8683c5 platform: andes/ae350: Add AE350 domain support
d682a0a docs: andes-ae350.md: Update ae350 documentation for fdt driver support
0fee0bf Makefile: Add cscope support
51acd49 docs/firmware: update the document
9d54f43 Makefile: Add rules for carray sources in lib/sbi
56bed1a lib: sbi_ecall: Generate extensions list with carray
22f38ee lib: sbi_ecall: Add Kconfig option for each extension
85cf56c lib: utils/fdt: Remove redundant code
21ba418 lib: utils/fdt: Simplified code
8e9966c docs: fix some typos
7b29264 lib: utils/serial: Fix semihosting compile error using LLVM
14f5c4c lib: sbi_ecall: Split up sbi_ecall_replace
8e63716 firmware: payloads: Optimize usage of "ALIGN"
1b0d71b platform: generic/allwinner: Remove unused header files
9a740f5 platform: generic/allwinner: Remove ghostly type cast
ba32021 Makefile: replace `echo` with `printf` for compatibility
49b0e35 Makefile: bugfix for handling platform paths
74e2029 lib: sbi: Simplified mmio match checking
fc82e84 lib: sbi: Fix is_region_valid()
f8eec91 lib: simplify fdt_parse_plmt_node()
cc54184 lib: simplify fdt_parse_plicsw_node()
e9bc7f1 lib: fix fdt_parse_plmt_node()
5daa0ef lib: fix fdt_parse_plicsw_node()
1f6866e lib: simplify fdt_translate_address()
ad2ac29 lib: fix fdt_parse_aclint_node()
cfbabb9 firmware: Minor optimization for relocate
a36d455 platform: generic/andes: Enable generic platform support for AE350
6cd4b9b docs: platform: Update AE350 and generic platform documentation
d3fcff7 docs: andes-ae350.md: fix watchdog nodename in dts example
4640d04 scripts/create-binary-archive.sh: remove andes/ae350 build directory
e977512 lib: utils: Add fdt_fixup_node() helper function
e1a0cb0 gitignore: add vim swap files
ed8b8f5 platform: generic: Make use of fdt_match_node()
8b00be6 lib: fix is_region_valid()
c2be214 lib: fix __fdt_parse_region()
7b08778 lib: fix irqchip_plic_update_hartid_table
cb568b9 lib: sbi: Synchronize PMP settings with virtual memory system
506928a scripts: use env to invoke bash
64e8b9f lib: utils: serial: Add Renesas SCIF driver
0021b43 lib: utils: serial: Add FDT driver for Renesas SCIF
6840902 lib: utils/irqchip: Add compatible string for Andestech NCEPLIC100
8b1617d platform: generic: Add Renesas RZ/Five initial support
7a3354a docs: platform: Add documentation for Renesas RZ/Five SoC
34da663 lib: utils/irqchip: plic: Fix the off-by-one error in priority 
save/restore helpers
8509e46 lib: utils/irqchip: plic: Ensure no out-of-bound access in priority 
save/restore helpers
91c8a7d lib: utils/irqchip: plic: Fix the off-by-one error in 
plic_context_init()
fabbc00 lib: utils/irqchip: plic: Fix the off-by-one error in context 
save/restore helpers
9a2eeb4 lib: utils/irqchip: plic: Ensure no out-of-bound access in context 
save/restore helpers
a8ee82c lib: utils/ipi: mswi: add T-Head C9xx CLINT compatible
ca7810a lib: utils/timer: mtimer: add a quirk for lacking mtime register
b848d87 lib: utils/timer: mtimer: add T-Head C9xx CLINT compatible
391ec85 docs: pmu: fix binding example
0412460 docs: pmu: update a reference to a deprecated property name
d5d12a9 docs: pmu: Update the pmu doc with removal of mcountinhbit restriction
6b5188c include: Bump-up version to 1.2

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: <20230207044003.3669059-1-bmeng@tinylab.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>


  Commit: f5c16685435c7f7fad399858dbfdeba69fcbd549
      
https://github.com/qemu/qemu/commit/f5c16685435c7f7fad399858dbfdeba69fcbd549
  Author: Frank Chang <frank.chang@sifive.com>
  Date:   2023-02-16 (Thu, 16 Feb 2023)

  Changed paths:
    M target/riscv/cpu.c
    M target/riscv/csr.c

  Log Message:
  -----------
  target/riscv: Remove privileged spec version restriction for RVV

The RVV specification does not require that the core needs to support
the privileged specification v1.12.0 to support RVV, and there is no
dependency from ISA level.

This commit removes the restriction from both RVV CSRs and extension CPU
ISA string.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230208063209.27279-1-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>


  Commit: a2453b8702ae59d5d5cd4c6380912083d19ebcc9
      
https://github.com/qemu/qemu/commit/a2453b8702ae59d5d5cd4c6380912083d19ebcc9
  Author: Alistair Francis <alistair.francis@wdc.com>
  Date:   2023-02-16 (Thu, 16 Feb 2023)

  Changed paths:
    M MAINTAINERS

  Log Message:
  -----------
  MAINTAINERS: Add some RISC-V reviewers

This patch adds some active RISC-V members as reviewers to the
MAINTAINERS file.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Acked-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Acked-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-Id: <20230209003308.738237-1-alistair.francis@opensource.wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>


  Commit: ed2898258689691f05616f8bdff08224ec799bac
      
https://github.com/qemu/qemu/commit/ed2898258689691f05616f8bdff08224ec799bac
  Author: Himanshu Chauhan <hchauhan@ventanamicro.com>
  Date:   2023-02-16 (Thu, 16 Feb 2023)

  Changed paths:
    M target/riscv/pmp.c

  Log Message:
  -----------
  target/riscv: Smepmp: Skip applying default rules when address matches

When MSECCFG.MML is set, after checking the address range in PMP if the
asked permissions are not same as programmed in PMP, the default
permissions are applied. This should only be the case when there
is no matching address is found.

This patch skips applying default rules when matching address range
is found. It returns the index of the match PMP entry.

Fixes: 824cac681c3 (target/riscv: Fix PMP propagation for tlb)
Signed-off-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230209055206.229392-1-hchauhan@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>


  Commit: f14e9acf9d7e9f5132d3dc1549d5c9ca1f951894
      
https://github.com/qemu/qemu/commit/f14e9acf9d7e9f5132d3dc1549d5c9ca1f951894
  Author: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
  Date:   2023-02-16 (Thu, 16 Feb 2023)

  Changed paths:
    M target/riscv/cpu_helper.c

  Log Message:
  -----------
  target/riscv: avoid env_archcpu() in cpu_get_tb_cpu_state()

We have a RISCVCPU *cpu pointer available at the start of the function.

Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-ID: <20230210123836.506286-1-dbarboza@ventanamicro.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>


  Commit: e8c0697d79ef05aa5aefb1121dfede59855556b4
      
https://github.com/qemu/qemu/commit/e8c0697d79ef05aa5aefb1121dfede59855556b4
  Author: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
  Date:   2023-02-16 (Thu, 16 Feb 2023)

  Changed paths:
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  target/riscv: Fix vslide1up.vf and vslide1down.vf

vslide1up_##BITWIDTH is used by the vslide1up.vx and vslide1up.vf. So its
scalar input should be uint64_t to hold the 64 bits float register.And the
same for vslide1down_##BITWIDTH.

This bug is caught when run these instructions on qemu-riscv32.

Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-ID: <20230213094550.29621-1-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>


  Commit: 51c9fb64a0334d8b6d5cdf6c2b05a594f3c2dca5
      
https://github.com/qemu/qemu/commit/51c9fb64a0334d8b6d5cdf6c2b05a594f3c2dca5
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2023-02-21 (Tue, 21 Feb 2023)

  Changed paths:
    M MAINTAINERS
    M hw/riscv/boot.c
    M hw/riscv/microchip_pfsoc.c
    M hw/riscv/opentitan.c
    M hw/riscv/sifive_e.c
    M hw/riscv/sifive_u.c
    M hw/riscv/spike.c
    M hw/riscv/virt.c
    M include/hw/riscv/boot.h
    M pc-bios/opensbi-riscv32-generic-fw_dynamic.bin
    M pc-bios/opensbi-riscv64-generic-fw_dynamic.bin
    M roms/opensbi
    M target/riscv/cpu.c
    M target/riscv/cpu_helper.c
    M target/riscv/csr.c
    M target/riscv/pmp.c
    M target/riscv/vector_helper.c

  Log Message:
  -----------
  Merge tag 'pull-riscv-to-apply-20230217' of 
https://github.com/palmer-dabbelt/qemu into staging

Fourth RISC-V PR for QEMU 8.0

* A triplet of cleanups to the kernel/initrd loader that avoids
  duplication between the various boards.
* OpenSBI has been updated to version 1.2.
* Weiwei Li, Daniel Henrique Barboza, and Liu Zhiwei have been added as
  reviewers.  Thanks for the help!
* A fix for PMP matching to avoid incorrectly appling the default
  permissions on PMP permission violations.
* A cleanup to avoid an unnecessary avoid env_archcpu() in
  cpu_get_tb_cpu_state().
* Fixes for the vector slide instructions to avoid truncating 64-bit
  values (such as doubles) on 32-bit targets.

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# 1MNhTgvuqs1kTEP/2J9h/s9pD5QmKMOyUvUfOJI0TkmpooPin7ueRYM3pm1WN9ue
# Co8ZeqwsqjvfmXqGl4yD2jQaIVGro7BzKjJECJWmyrUXmQ1DJyigdfkPRG1d5WpB
# 7RWD5A75dHBDItO/sX4bpWOHING/JrSz2QxBE4QE+fqB8uQ1iyUFuH2a27DlwAwm
# HPZCo2v9AvUxqu+vQLQbE4EHvp7EjvPEp+yE5lq2weXvKWtmf6fniOGo0uYgpdXE
# TgCRzpODrHoSoE6TNQ0IO76leqTbCoWTdGgq9/f5392t980rk86SV3f5dpjDo26a
# VlCFRKfhXrWmf8HXBlY1+S8bZhCY92AS9tWlTUhC2RV08ZUAhAPINvdxvpoPhEVd
# AvU0QS2+YPeS0w==
# =45cK
# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 17 Feb 2023 17:34:23 GMT
# gpg:                using RSA key 2B3C3747446843B24A943A7A2E1319F35FBB1889
# gpg:                issuer "palmer@dabbelt.com"
# gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>" [unknown]
# gpg:                 aka "Palmer Dabbelt <palmerdabbelt@google.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 00CE 76D1 8349 60DF CE88  6DF8 EF4C A150 2CCB AB41
#      Subkey fingerprint: 2B3C 3747 4468 43B2 4A94  3A7A 2E13 19F3 5FBB 1889

* tag 'pull-riscv-to-apply-20230217' of https://github.com/palmer-dabbelt/qemu:
  target/riscv: Fix vslide1up.vf and vslide1down.vf
  target/riscv: avoid env_archcpu() in cpu_get_tb_cpu_state()
  target/riscv: Smepmp: Skip applying default rules when address matches
  MAINTAINERS: Add some RISC-V reviewers
  target/riscv: Remove privileged spec version restriction for RVV
  roms/opensbi: Upgrade from v1.1 to v1.2
  hw/riscv/boot.c: make riscv_load_initrd() static
  hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel()
  hw/riscv: handle 32 bit CPUs kernel_entry in riscv_load_kernel()

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/1ff778872360...51c9fb64a033
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