[Qemu-commits] [qemu/qemu] 65e57f: target/tricore: Fix OPC2_32_RCRW_IMASK translation

[Peter Maydell]

  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 65e57fdb25a0df8950f107041550aeb178af41ad
      
https://github.com/qemu/qemu/commit/65e57fdb25a0df8950f107041550aeb178af41ad
  Author: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
  Date:   2023-02-08 (Wed, 08 Feb 2023)

  Changed paths:
    M target/tricore/translate.c

  Log Message:
  -----------
  target/tricore: Fix OPC2_32_RCRW_IMASK translation

we were mixing up the "c" and "d" registers. We used "d" as a
destination register und "c" as the source. According to the TriCore ISA
manual 1.6 vol 2 it is the other way round.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/653
Message-Id: <20230202120432.1268-2-kbastian@mail.uni-paderborn.de>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>


  Commit: 76f7f54840abef8f712e51d87ecb38f27a0d9db0
      
https://github.com/qemu/qemu/commit/76f7f54840abef8f712e51d87ecb38f27a0d9db0
  Author: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
  Date:   2023-02-08 (Wed, 08 Feb 2023)

  Changed paths:
    M tests/tcg/tricore/Makefile.softmmu-target
    M tests/tcg/tricore/macros.h
    A tests/tcg/tricore/test_imask.S

  Log Message:
  -----------
  tests/tcg/tricore: Add test for OPC2_32_RCRW_IMASK

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20230202120432.1268-3-kbastian@mail.uni-paderborn.de>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>


  Commit: 1c6b2e4b794d460a16a7f94cf6a7d6864f708be1
      
https://github.com/qemu/qemu/commit/1c6b2e4b794d460a16a7f94cf6a7d6864f708be1
  Author: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
  Date:   2023-02-08 (Wed, 08 Feb 2023)

  Changed paths:
    M target/tricore/translate.c

  Log Message:
  -----------
  target/tricore: Fix OPC2_32_RCRW_INSERT translation

we were mixing up the "c" and "d" registers. We used "d" as a
destination register und "c" as the source. According to the TriCore ISA
manual 1.6 vol 2 it is the other way round.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/653
Message-Id: <20230202120432.1268-4-kbastian@mail.uni-paderborn.de>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>


  Commit: fa581531ffdc94ba18da6ec0c566bece57a60a85
      
https://github.com/qemu/qemu/commit/fa581531ffdc94ba18da6ec0c566bece57a60a85
  Author: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
  Date:   2023-02-08 (Wed, 08 Feb 2023)

  Changed paths:
    M tests/tcg/tricore/Makefile.softmmu-target
    M tests/tcg/tricore/macros.h
    A tests/tcg/tricore/test_insert.S

  Log Message:
  -----------
  tests/tcg/tricore: Add test for OPC2_32_RCRW_INSERT

DREG_RS2 and DREG_CALC_RESULT were mapped to the same register which
would not trigger https://gitlab.com/qemu-project/qemu/-/issues/653. So
let's make each register unique.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20230202120432.1268-5-kbastian@mail.uni-paderborn.de>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>


  Commit: 48bffe7f6b65e78d84ffae0e4385af1aa935767c
      
https://github.com/qemu/qemu/commit/48bffe7f6b65e78d84ffae0e4385af1aa935767c
  Author: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
  Date:   2023-02-08 (Wed, 08 Feb 2023)

  Changed paths:
    M target/tricore/translate.c

  Log Message:
  -----------
  target/tricore: Fix RRPW_DEXTR

if we used const16 == 0 we would crash qemu with the error:
../tcg/tcg-op.c:196: tcg_gen_shri_i32: Assertion `arg2 >= 0 && arg2 < 32' failed

This whole instruction can be handled by 'tcg_gen_extract2_tl' which
takes care of this special case as well.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20230202120432.1268-6-kbastian@mail.uni-paderborn.de>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>


  Commit: 70447df9365c9401643e4260436c64b35aab003e
      
https://github.com/qemu/qemu/commit/70447df9365c9401643e4260436c64b35aab003e
  Author: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
  Date:   2023-02-08 (Wed, 08 Feb 2023)

  Changed paths:
    M tests/tcg/tricore/Makefile.softmmu-target
    M tests/tcg/tricore/macros.h
    A tests/tcg/tricore/test_dextr.S

  Log Message:
  -----------
  tests/tcg/tricore: Add tests for RRPW_DEXTR

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20230202120432.1268-7-kbastian@mail.uni-paderborn.de>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>


  Commit: a4d5d153c4c53076cea70c1609f3d7427322586b
      
https://github.com/qemu/qemu/commit/a4d5d153c4c53076cea70c1609f3d7427322586b
  Author: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
  Date:   2023-02-08 (Wed, 08 Feb 2023)

  Changed paths:
    M target/tricore/translate.c

  Log Message:
  -----------
  target/tricore: Fix OPC2_32_RRRR_DEXTR

if cpu_gpr_d[r3] == 0 then we were shifting the lower register to the
right by 32 which is undefined behaviour. In this case the TriCore would
do nothing an just return the higher register cpu_reg_d[r1]. We fixed
that by detecting whether cpu_gpr_d[r3] was zero and cleared the lower
register.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20230202120432.1268-8-kbastian@mail.uni-paderborn.de>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>


  Commit: 7ebe4cb36433af7aaaf621e851784f89b8cc5cb8
      
https://github.com/qemu/qemu/commit/7ebe4cb36433af7aaaf621e851784f89b8cc5cb8
  Author: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
  Date:   2023-02-08 (Wed, 08 Feb 2023)

  Changed paths:
    M tests/tcg/tricore/macros.h
    M tests/tcg/tricore/test_dextr.S

  Log Message:
  -----------
  tests/tcg/tricore: Add OPC2_32_RRRR_DEXTR tests

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20230202120432.1268-9-kbastian@mail.uni-paderborn.de>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>


  Commit: d8b33554d8dd9ee6348839d9e4d6f93adf45eff1
      
https://github.com/qemu/qemu/commit/d8b33554d8dd9ee6348839d9e4d6f93adf45eff1
  Author: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
  Date:   2023-02-08 (Wed, 08 Feb 2023)

  Changed paths:
    M target/tricore/translate.c

  Log Message:
  -----------
  target/tricore: Fix OPC2_32_BO_LD_BU_PREINC

we were sign extending the result of the load, while the instruction
clearly states that the result should be unsigned.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20230202120432.1268-10-kbastian@mail.uni-paderborn.de>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>


  Commit: 6dcb9922f3dd6d7f7129621f7a10acead32dcbb0
      
https://github.com/qemu/qemu/commit/6dcb9922f3dd6d7f7129621f7a10acead32dcbb0
  Author: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
  Date:   2023-02-08 (Wed, 08 Feb 2023)

  Changed paths:
    M tests/tcg/tricore/Makefile.softmmu-target
    M tests/tcg/tricore/macros.h
    A tests/tcg/tricore/test_ld_bu.S

  Log Message:
  -----------
  tests/tcg/tricore: Add LD.BU tests

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20230202120432.1268-11-kbastian@mail.uni-paderborn.de>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>


  Commit: 77eb0085c8fe48e77f845d9db0d3c4c4ccf7c4f1
      
https://github.com/qemu/qemu/commit/77eb0085c8fe48e77f845d9db0d3c4c4ccf7c4f1
  Author: Anton Kochkov <anton.kochkov@proton.me>
  Date:   2023-02-08 (Wed, 08 Feb 2023)

  Changed paths:
    M target/tricore/translate.c

  Log Message:
  -----------
  target/tricore: Fix OPC1_16_SRO_LD_H translation

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Eitan Eliahu <eitan_eliahu@hotmail.com>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/652
Message-Id: <20230112142258.514079-1-anton.kochkov@proton.me>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>


  Commit: 6e34f54d88184b25db4fbc4dd1665d9be1a9e21c
      
https://github.com/qemu/qemu/commit/6e34f54d88184b25db4fbc4dd1665d9be1a9e21c
  Author: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
  Date:   2023-02-08 (Wed, 08 Feb 2023)

  Changed paths:
    M tests/tcg/tricore/Makefile.softmmu-target
    M tests/tcg/tricore/macros.h
    A tests/tcg/tricore/test_ld_h.S

  Log Message:
  -----------
  tests/tcg/tricore: Add test for ld.h

this exercises the error reported in
https://gitlab.com/qemu-project/qemu/-/issues/652.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20230203132132.511254-1-kbastian@mail.uni-paderborn.de>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>


  Commit: 65417c2357b6ca0d33310e0f081ee27647987df8
      
https://github.com/qemu/qemu/commit/65417c2357b6ca0d33310e0f081ee27647987df8
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2023-02-08 (Wed, 08 Feb 2023)

  Changed paths:
    M target/tricore/translate.c
    M tests/tcg/tricore/Makefile.softmmu-target
    M tests/tcg/tricore/macros.h
    A tests/tcg/tricore/test_dextr.S
    A tests/tcg/tricore/test_imask.S
    A tests/tcg/tricore/test_insert.S
    A tests/tcg/tricore/test_ld_bu.S
    A tests/tcg/tricore/test_ld_h.S

  Log Message:
  -----------
  Merge tag 'pull-tricore-20230208' of https://github.com/bkoppelmann/qemu into 
staging

tricore insn bugfixes for qemu 8.0

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* tag 'pull-tricore-20230208' of https://github.com/bkoppelmann/qemu:
  tests/tcg/tricore: Add test for ld.h
  target/tricore: Fix OPC1_16_SRO_LD_H translation
  tests/tcg/tricore: Add LD.BU tests
  target/tricore: Fix OPC2_32_BO_LD_BU_PREINC
  tests/tcg/tricore: Add OPC2_32_RRRR_DEXTR tests
  target/tricore: Fix OPC2_32_RRRR_DEXTR
  tests/tcg/tricore: Add tests for RRPW_DEXTR
  target/tricore: Fix RRPW_DEXTR
  tests/tcg/tricore: Add test for OPC2_32_RCRW_INSERT
  target/tricore: Fix OPC2_32_RCRW_INSERT translation
  tests/tcg/tricore: Add test for OPC2_32_RCRW_IMASK
  target/tricore: Fix OPC2_32_RCRW_IMASK translation

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


Compare: https://github.com/qemu/qemu/compare/ae2b5d8381a7...65417c2357b6